955402c393050be7e20b6aafd4de9d4901c40ee6
5 from litex
.build
.generic_platform
import tools
6 from litex
.soc
.integration
.soc_core
import *
7 from litex
.soc
.integration
.cpu_interface
import get_csr_header
8 from litex
.soc
.interconnect
import wishbone
9 from litex
.soc
.interconnect
import axi
12 class SoCZynq(SoCCore
):
13 SoCCore
.mem_map
["csr"] = 0x00000000
14 def __init__(self
, platform
, clk_freq
, ps7_name
, **kwargs
):
15 SoCCore
.__init
__(self
, platform
, clk_freq
, cpu_type
=None, shadow_base
=0x00000000, **kwargs
)
17 # PS7 --------------------------------------------------------------------------------------
18 self
.axi_gp0
= axi_gp0
= axi
.AXIInterface(data_width
=32, address_width
=32, id_width
=12)
19 ps7_ddram_pads
= platform
.request("ps7_ddram")
20 self
.specials
+= Instance(ps7_name
,
22 io_PS_CLK
=platform
.request("ps7_clk"),
23 io_PS_PORB
=platform
.request("ps7_porb"),
24 io_PS_SRSTB
=platform
.request("ps7_srstb"),
27 io_MIO
=platform
.request("ps7_mio"),
30 io_DDR_Addr
=ps7_ddram_pads
.addr
,
31 io_DDR_BankAddr
=ps7_ddram_pads
.ba
,
32 io_DDR_CAS_n
=ps7_ddram_pads
.cas_n
,
33 io_DDR_Clk_n
=ps7_ddram_pads
.ck_n
,
34 io_DDR_Clk
=ps7_ddram_pads
.ck_p
,
35 io_DDR_CKE
=ps7_ddram_pads
.cke
,
36 io_DDR_CS_n
=ps7_ddram_pads
.cs_n
,
37 io_DDR_DM
=ps7_ddram_pads
.dm
,
38 io_DDR_DQ
=ps7_ddram_pads
.dq
,
39 io_DDR_DQS_n
=ps7_ddram_pads
.dqs_n
,
40 io_DDR_DQS
=ps7_ddram_pads
.dqs_p
,
41 io_DDR_ODT
=ps7_ddram_pads
.odt
,
42 io_DDR_RAS_n
=ps7_ddram_pads
.ras_n
,
43 io_DDR_DRSTB
=ps7_ddram_pads
.reset_n
,
44 io_DDR_WEB
=ps7_ddram_pads
.we_n
,
45 io_DDR_VRN
=ps7_ddram_pads
.vrn
,
46 io_DDR_VRP
=ps7_ddram_pads
.vrp
,
55 i_USB0_VBUS_PWRFAULT
=0,
58 o_FCLK_CLK0
=ClockSignal("sys"),
61 i_M_AXI_GP0_ACLK
=ClockSignal("sys"),
64 o_M_AXI_GP0_AWVALID
=axi_gp0
.aw
.valid
,
65 i_M_AXI_GP0_AWREADY
=axi_gp0
.aw
.ready
,
66 o_M_AXI_GP0_AWADDR
=axi_gp0
.aw
.addr
,
67 o_M_AXI_GP0_AWBURST
=axi_gp0
.aw
.burst
,
68 o_M_AXI_GP0_AWLEN
=axi_gp0
.aw
.len,
69 o_M_AXI_GP0_AWSIZE
=axi_gp0
.aw
.size
,
70 o_M_AXI_GP0_AWID
=axi_gp0
.aw
.id,
71 #o_M_AXI_GP0_AWLOCK =,
72 #o_M_AXI_GP0_AWPROT =,
73 #o_M_AXI_GP0_AWCACHE =,
77 o_M_AXI_GP0_WVALID
=axi_gp0
.w
.valid
,
78 o_M_AXI_GP0_WLAST
=axi_gp0
.w
.last
,
79 i_M_AXI_GP0_WREADY
=axi_gp0
.w
.ready
,
81 o_M_AXI_GP0_WDATA
=axi_gp0
.w
.data
,
82 o_M_AXI_GP0_WSTRB
=axi_gp0
.w
.strb
,
85 i_M_AXI_GP0_BVALID
=axi_gp0
.b
.valid
,
86 o_M_AXI_GP0_BREADY
=axi_gp0
.b
.ready
,
87 i_M_AXI_GP0_BID
=axi_gp0
.b
.id,
88 i_M_AXI_GP0_BRESP
=axi_gp0
.b
.resp
,
91 o_M_AXI_GP0_ARVALID
=axi_gp0
.ar
.valid
,
92 i_M_AXI_GP0_ARREADY
=axi_gp0
.ar
.ready
,
93 o_M_AXI_GP0_ARADDR
=axi_gp0
.ar
.addr
,
94 o_M_AXI_GP0_ARBURST
=axi_gp0
.ar
.burst
,
95 o_M_AXI_GP0_ARLEN
=axi_gp0
.ar
.len,
96 o_M_AXI_GP0_ARID
=axi_gp0
.ar
.id,
100 #o_M_AXI_GP0_ARCACHE=,
104 i_M_AXI_GP0_RVALID
=axi_gp0
.r
.valid
,
105 o_M_AXI_GP0_RREADY
=axi_gp0
.r
.ready
,
106 i_M_AXI_GP0_RLAST
=axi_gp0
.r
.last
,
107 i_M_AXI_GP0_RID
=axi_gp0
.r
.id,
108 i_M_AXI_GP0_RRESP
=axi_gp0
.r
.resp
,
109 i_M_AXI_GP0_RDATA
=axi_gp0
.r
.data
,
111 platform
.add_ip(os
.path
.join("ip", ps7_name
+ ".xci"))
113 # AXI to Wishbone --------------------------------------------------------------------------
114 self
.wb_gp0
= wb_gp0
= wishbone
.Interface()
115 axi2wishbone
= axi
.AXI2Wishbone(axi_gp0
, wb_gp0
, base_address
=0x43c00000)
116 self
.submodules
+= axi2wishbone
117 self
.add_wb_master(wb_gp0
)
119 def generate_software_header(self
, filename
):
120 csr_header
= get_csr_header(self
.get_csr_regions(),
121 self
.get_constants(),
122 with_access_functions
=False)
123 tools
.write_to_file(filename
, csr_header
)