litex/soc/misoc/cores/liteeth_mini/phy/loopback.py

   1 from migen import *
   2
   3 from misoc.interconnect.csr import *
   4 from misoc.interconnect.stream import *
   5 from misoc.cores.liteeth_mini.common import *
   6 from misoc.cores.liteeth.mini.generic import *
   7
   8
   9 class LiteEthPHYLoopbackCRG(Module, AutoCSR):
  10     def __init__(self):
  11         self._reset = CSRStorage()
  12
  13         # # #
  14
  15         self.clock_domains.cd_eth_rx = ClockDomain()
  16         self.clock_domains.cd_eth_tx = ClockDomain()
  17         self.comb += [
  18             self.cd_eth_rx.clk.eq(ClockSignal()),
  19             self.cd_eth_tx.clk.eq(ClockSignal())
  20         ]
  21
  22         reset = self._reset.storage
  23         self.comb += [
  24             self.cd_eth_rx.rst.eq(reset),
  25             self.cd_eth_tx.rst.eq(reset)
  26         ]
  27
  28
  29 class LiteEthPHYLoopback(Module, AutoCSR):
  30     def __init__(self):
  31         self.dw = 8
  32         self.submodules.crg = LiteEthLoopbackPHYCRG()
  33         self.sink = Sink(eth_phy_description(8))
  34         self.source = Source(eth_phy_description(8))
  35         self.comb += Record.connect(self.sink, self.source)