litex/soc/misoc/interconnect/dfi.py

   1 from migen import *
   2 from migen.genlib.record import *
   3
   4
   5 def phase_cmd_description(addressbits, bankbits):
   6     return [
   7         ("address", addressbits, DIR_M_TO_S),
   8         ("bank",       bankbits, DIR_M_TO_S),
   9         ("cas_n",             1, DIR_M_TO_S),
  10         ("cs_n",              1, DIR_M_TO_S),
  11         ("ras_n",             1, DIR_M_TO_S),
  12         ("we_n",              1, DIR_M_TO_S),
  13         ("cke",               1, DIR_M_TO_S),
  14         ("odt",               1, DIR_M_TO_S),
  15         ("reset_n",           1, DIR_M_TO_S)
  16     ]
  17
  18
  19 def phase_wrdata_description(databits):
  20     return [
  21         ("wrdata",         databits, DIR_M_TO_S),
  22         ("wrdata_en",             1, DIR_M_TO_S),
  23         ("wrdata_mask", databits//8, DIR_M_TO_S)
  24     ]
  25
  26
  27 def phase_rddata_description(databits):
  28     return [
  29         ("rddata_en",           1, DIR_M_TO_S),
  30         ("rddata",       databits, DIR_S_TO_M),
  31         ("rddata_valid",        1, DIR_S_TO_M)
  32     ]
  33
  34
  35 def phase_description(addressbits, bankbits, databits):
  36     r = phase_cmd_description(addressbits, bankbits)
  37     r += phase_wrdata_description(databits)
  38     r += phase_rddata_description(databits)
  39     return r
  40
  41
  42 class Interface(Record):
  43     def __init__(self, addressbits, bankbits, databits, nphases=1):
  44         layout = [("p"+str(i), phase_description(addressbits, bankbits, databits)) for i in range(nphases)]
  45         Record.__init__(self, layout)
  46         self.phases = [getattr(self, "p"+str(i)) for i in range(nphases)]
  47         for p in self.phases:
  48             p.cas_n.reset = 1
  49             p.cs_n.reset = 1
  50             p.ras_n.reset = 1
  51             p.we_n.reset = 1
  52
  53     # Returns pairs (DFI-mandated signal name, Migen signal object)
  54     def get_standard_names(self, m2s=True, s2m=True):
  55         r = []
  56         add_suffix = len(self.phases) > 1
  57         for n, phase in enumerate(self.phases):
  58             for field, size, direction in phase.layout:
  59                 if (m2s and direction == DIR_M_TO_S) or (s2m and direction == DIR_S_TO_M):
  60                     if add_suffix:
  61                         if direction == DIR_M_TO_S:
  62                             suffix = "_p" + str(n)
  63                         else:
  64                             suffix = "_w" + str(n)
  65                     else:
  66                         suffix = ""
  67                     r.append(("dfi_" + field + suffix, getattr(phase, field)))
  68         return r
  69
  70
  71 class Interconnect(Module):
  72     def __init__(self, master, slave):
  73         self.comb += master.connect(slave)