litex/soc/misoc/targets/minispartan6.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4 from fractions import Fraction
   5
   6 from migen import *
   7 from migen.genlib.resetsync import AsyncResetSynchronizer
   8 from migen.build.platforms import minispartan6
   9
  10 from misoc.cores.sdram_settings import AS4C16M16
  11 from misoc.cores.sdram_phy import GENSDRPHY
  12 from misoc.integration.soc_sdram import *
  13 from misoc.integration.builder import *
  14
  15
  16 class _CRG(Module):
  17     def __init__(self, platform, clk_freq):
  18         self.clock_domains.cd_sys = ClockDomain()
  19         self.clock_domains.cd_sys_ps = ClockDomain()
  20
  21         f0 = 32*1000000
  22         clk32 = platform.request("clk32")
  23         clk32a = Signal()
  24         self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
  25         clk32b = Signal()
  26         self.specials += Instance("BUFIO2", p_DIVIDE=1,
  27                                   p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
  28                                   i_I=clk32a, o_DIVCLK=clk32b)
  29         f = Fraction(int(clk_freq), int(f0))
  30         n, m, p = f.denominator, f.numerator, 8
  31         assert f0/n*m == clk_freq
  32         pll_lckd = Signal()
  33         pll_fb = Signal()
  34         pll = Signal(6)
  35         self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
  36                                      p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
  37                                      p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
  38                                      i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
  39                                      p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
  40                                      i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
  41                                      p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
  42                                      i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
  43                                      o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
  44                                      o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
  45                                      o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
  46                                      o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
  47                                      o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
  48                                      o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
  49                                      p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
  50                                      p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
  51                                      p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
  52                                      p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
  53                                      p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,  # sys
  54                                      p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1,  # sys_ps
  55         )
  56         self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
  57         self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
  58         self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
  59
  60         self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
  61                                   p_INIT=0, p_SRTYPE="SYNC",
  62                                   i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
  63                                   i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
  64                                   o_Q=platform.request("sdram_clock"))
  65
  66
  67 class BaseSoC(SoCSDRAM):
  68     def __init__(self, **kwargs):
  69         clk_freq = 80*1000000
  70         platform = minispartan6.Platform()
  71         SoCSDRAM.__init__(self, platform, clk_freq,
  72                           integrated_rom_size=0x8000,
  73                           **kwargs)
  74
  75         self.submodules.crg = _CRG(platform, clk_freq)
  76
  77         if not self.integrated_main_ram_size:
  78             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
  79             sdram_module = AS4C16M16(clk_freq)
  80             self.register_sdram(self.sdrphy, "minicon",
  81                                 sdram_module.geom_settings, sdram_module.timing_settings)
  82
  83
  84 def main():
  85     parser = argparse.ArgumentParser(description="MiSoC port to the MiniSpartan6")
  86     builder_args(parser)
  87     soc_sdram_args(parser)
  88     args = parser.parse_args()
  89
  90     soc = BaseSoC(**soc_sdram_argdict(args))
  91     builder = Builder(soc, **builder_argdict(args))
  92     builder.build()
  93
  94
  95 if __name__ == "__main__":
  96     main()