litex/soc/misoc/targets/simple.py

   1 #!/usr/bin/env python3
   2
   3 import argparse
   4 import importlib
   5
   6 from migen import *
   7 from migen.genlib.io import CRG
   8
   9 from misoc.cores.liteeth_mini.phy import LiteEthPHY
  10 from misoc.cores.liteeth_mini.mac import LiteEthMAC
  11 from misoc.integration.soc_core import *
  12 from misoc.integration.builder import *
  13
  14
  15 class BaseSoC(SoCCore):
  16     def __init__(self, platform, **kwargs):
  17         SoCCore.__init__(self, platform,
  18             clk_freq=int((1/(platform.default_clk_period))*1000000000),
  19             integrated_rom_size=0x8000,
  20             integrated_main_ram_size=16*1024,
  21             **kwargs)
  22         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
  23
  24
  25 class MiniSoC(BaseSoC):
  26     csr_map = {
  27         "ethphy": 20,
  28         "ethmac": 21
  29     }
  30     csr_map.update(BaseSoC.csr_map)
  31
  32     interrupt_map = {
  33         "ethmac": 2,
  34     }
  35     interrupt_map.update(BaseSoC.interrupt_map)
  36
  37     mem_map = {
  38         "ethmac": 0x30000000,  # (shadow @0xb0000000)
  39     }
  40     mem_map.update(BaseSoC.mem_map)
  41
  42     def __init__(self, platform, **kwargs):
  43         BaseSoC.__init__(self, platform, **kwargs)
  44
  45         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
  46                                             platform.request("eth"))
  47         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
  48                                             interface="wishbone",
  49                                             with_preamble_crc=False)
  50         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
  51         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
  52
  53
  54 def main():
  55     parser = argparse.ArgumentParser(description="Generic MiSoC port")
  56     builder_args(parser)
  57     soc_core_args(parser)
  58     parser.add_argument("--with-ethernet", action="store_true",
  59                         help="enable Ethernet support")
  60     parser.add_argument("platform",
  61                         help="module name of the Migen platform to build for")
  62     args = parser.parse_args()
  63
  64     platform_module = importlib.import_module(args.platform)
  65     platform = platform_module.Platform()
  66     cls = MiniSoC if args.with_ethernet else BaseSoC
  67     soc = cls(platform, **soc_core_argdict(args))
  68     builder = Builder(soc, **builder_argdict(args))
  69     builder.build()
  70
  71
  72 if __name__ == "__main__":
  73     main()