1 #include <generated/csr.h>
7 #include <generated/sdram_phy.h>
8 #include <generated/mem.h>
14 static void cdelay(int i
)
17 #if defined (__lm32__)
18 __asm__
volatile("nop");
19 #elif defined (__or1k__)
20 __asm__
volatile("l.nop");
21 #elif defined (__picorv32__)
22 __asm__
volatile("nop");
23 #elif defined (__vexriscv__)
24 __asm__
volatile("nop");
25 #elif defined (__minerva__)
26 __asm__
volatile("nop");
28 #error Unsupported architecture
36 sdram_dfii_control_write(DFII_CONTROL_CKE
|DFII_CONTROL_ODT
|DFII_CONTROL_RESET_N
);
37 printf("SDRAM now under software control\n");
42 sdram_dfii_control_write(DFII_CONTROL_SEL
);
43 printf("SDRAM now under hardware control\n");
46 void sdrrow(char *_row
)
52 sdram_dfii_pi0_address_write(0x0000);
53 sdram_dfii_pi0_baddress_write(0);
54 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
56 printf("Precharged\n");
58 row
= strtoul(_row
, &c
, 0);
60 printf("incorrect row\n");
63 sdram_dfii_pi0_address_write(row
);
64 sdram_dfii_pi0_baddress_write(0);
65 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CS
);
67 printf("Activated row %d\n", row
);
80 first_byte
= DFII_PIX_DATA_SIZE
/2 - 1 - dq
;
81 step
= DFII_PIX_DATA_SIZE
/2;
84 for(p
=0;p
<DFII_NPHASES
;p
++)
85 for(i
=first_byte
;i
<DFII_PIX_DATA_SIZE
;i
+=step
)
86 printf("%02x", MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*i
));
90 void sdrrd(char *startaddr
, char *dq
)
97 printf("sdrrd <address>\n");
100 addr
= strtoul(startaddr
, &c
, 0);
102 printf("incorrect address\n");
108 _dq
= strtoul(dq
, &c
, 0);
110 printf("incorrect DQ\n");
115 sdram_dfii_pird_address_write(addr
);
116 sdram_dfii_pird_baddress_write(0);
117 command_prd(DFII_COMMAND_CAS
|DFII_COMMAND_CS
|DFII_COMMAND_RDDATA
);
122 void sdrrderr(char *count
)
128 unsigned char prev_data
[DFII_NPHASES
*DFII_PIX_DATA_SIZE
];
129 unsigned char errs
[DFII_NPHASES
*DFII_PIX_DATA_SIZE
];
132 printf("sdrrderr <count>\n");
135 _count
= strtoul(count
, &c
, 0);
137 printf("incorrect count\n");
141 for(i
=0;i
<DFII_NPHASES
*DFII_PIX_DATA_SIZE
;i
++)
143 for(addr
=0;addr
<16;addr
++) {
144 sdram_dfii_pird_address_write(addr
*8);
145 sdram_dfii_pird_baddress_write(0);
146 command_prd(DFII_COMMAND_CAS
|DFII_COMMAND_CS
|DFII_COMMAND_RDDATA
);
148 for(p
=0;p
<DFII_NPHASES
;p
++)
149 for(i
=0;i
<DFII_PIX_DATA_SIZE
;i
++)
150 prev_data
[p
*DFII_PIX_DATA_SIZE
+i
] = MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*i
);
152 for(j
=0;j
<_count
;j
++) {
153 command_prd(DFII_COMMAND_CAS
|DFII_COMMAND_CS
|DFII_COMMAND_RDDATA
);
155 for(p
=0;p
<DFII_NPHASES
;p
++)
156 for(i
=0;i
<DFII_PIX_DATA_SIZE
;i
++) {
157 unsigned char new_data
;
159 new_data
= MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*i
);
160 errs
[p
*DFII_PIX_DATA_SIZE
+i
] |= prev_data
[p
*DFII_PIX_DATA_SIZE
+i
] ^ new_data
;
161 prev_data
[p
*DFII_PIX_DATA_SIZE
+i
] = new_data
;
166 for(i
=0;i
<DFII_NPHASES
*DFII_PIX_DATA_SIZE
;i
++)
167 printf("%02x", errs
[i
]);
169 for(p
=0;p
<DFII_NPHASES
;p
++)
170 for(i
=0;i
<DFII_PIX_DATA_SIZE
;i
++)
171 printf("%2x", DFII_PIX_DATA_SIZE
/2 - 1 - (i
% (DFII_PIX_DATA_SIZE
/2)));
175 void sdrwr(char *startaddr
)
182 if(*startaddr
== 0) {
183 printf("sdrrd <address>\n");
186 addr
= strtoul(startaddr
, &c
, 0);
188 printf("incorrect address\n");
192 for(p
=0;p
<DFII_NPHASES
;p
++)
193 for(i
=0;i
<DFII_PIX_DATA_SIZE
;i
++)
194 MMPTR(sdram_dfii_pix_wrdata_addr
[p
]+4*i
) = 0x10*p
+ i
;
196 sdram_dfii_piwr_address_write(addr
);
197 sdram_dfii_piwr_baddress_write(0);
198 command_pwr(DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
|DFII_COMMAND_WRDATA
);
201 #ifdef CSR_DDRPHY_BASE
204 #define ERR_DDRPHY_DELAY 512
206 #define ERR_DDRPHY_DELAY 32
208 #define ERR_DDRPHY_BITSLIP 8
210 #ifdef CSR_DDRPHY_WLEVEL_EN_ADDR
214 sdram_dfii_pi0_address_write(DDR3_MR1
| (1 << 7));
215 sdram_dfii_pi0_baddress_write(1);
216 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
217 ddrphy_wlevel_en_write(1);
222 sdram_dfii_pi0_address_write(DDR3_MR1
);
223 sdram_dfii_pi0_baddress_write(1);
224 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
225 ddrphy_wlevel_en_write(0);
228 static void write_level_scan(void)
234 printf("Write leveling scan:\n");
238 for(i
=0;i
<DFII_PIX_DATA_SIZE
/2;i
++) {
240 dq_address
= sdram_dfii_pix_rddata_addr
[0]+4*(DFII_PIX_DATA_SIZE
/2-1-i
);
241 ddrphy_dly_sel_write(1 << i
);
242 ddrphy_wdly_dq_rst_write(1);
243 ddrphy_wdly_dqs_rst_write(1);
244 for(j
=0;j
<ERR_DDRPHY_DELAY
- ddrphy_half_sys8x_taps_read();j
++) {
245 ddrphy_wlevel_strobe_write(1);
247 dq
= MMPTR(dq_address
);
248 printf("%d", dq
!= 0);
249 ddrphy_wdly_dq_inc_write(1);
250 ddrphy_wdly_dqs_inc_write(1);
258 static int write_level(int *delay
, int *high_skew
)
266 err_ddrphy_wdly
= ERR_DDRPHY_DELAY
- ddrphy_half_sys8x_taps_read();
268 printf("Write leveling: ");
272 for(i
=0;i
<DFII_PIX_DATA_SIZE
/2;i
++) {
273 dq_address
= sdram_dfii_pix_rddata_addr
[0]+4*(DFII_PIX_DATA_SIZE
/2-1-i
);
274 ddrphy_dly_sel_write(1 << i
);
275 ddrphy_wdly_dq_rst_write(1);
276 ddrphy_wdly_dqs_rst_write(1);
277 #ifdef KUSDDRPHY /* Need to init manually on Ultrascale */
279 for(j
=0; j
<ddrphy_wdly_dqs_taps_read(); j
++)
280 ddrphy_wdly_dqs_inc_write(1);
285 ddrphy_wlevel_strobe_write(1);
287 dq
= MMPTR(dq_address
);
290 * Assume this DQ group has between 1 and 2 bit times of skew.
291 * Bring DQS into the CK=0 zone before continuing leveling.
293 #ifndef DDRPHY_HIGH_SKEW_DISABLE
297 if(delay
[i
] >= err_ddrphy_wdly
)
299 ddrphy_wdly_dq_inc_write(1);
300 ddrphy_wdly_dqs_inc_write(1);
301 ddrphy_wlevel_strobe_write(1);
303 dq
= MMPTR(dq_address
);
313 if(delay
[i
] >= err_ddrphy_wdly
)
315 ddrphy_wdly_dq_inc_write(1);
316 ddrphy_wdly_dqs_inc_write(1);
318 ddrphy_wlevel_strobe_write(1);
320 dq
= MMPTR(dq_address
);
326 for(i
=DFII_PIX_DATA_SIZE
/2-1;i
>=0;i
--) {
327 printf("%2d%c ", delay
[i
], high_skew
[i
] ? '*' : ' ');
328 if(delay
[i
] >= err_ddrphy_wdly
)
333 printf("completed\n");
340 #endif /* CSR_DDRPHY_WLEVEL_EN_ADDR */
342 static void read_bitslip_inc(char m
)
344 ddrphy_dly_sel_write(1 << m
);
346 ddrphy_rdly_dq_bitslip_write(1);
348 /* 7-series SERDES in DDR mode needs 3 pulses for 1 bitslip */
349 ddrphy_rdly_dq_bitslip_write(1);
350 ddrphy_rdly_dq_bitslip_write(1);
351 ddrphy_rdly_dq_bitslip_write(1);
355 static void read_bitslip(int *delay
, int *high_skew
)
360 bitslip_thr
= 0x7fffffff;
361 for(i
=0;i
<DFII_PIX_DATA_SIZE
/2;i
++)
362 if(high_skew
[i
] && (delay
[i
] < bitslip_thr
))
363 bitslip_thr
= delay
[i
];
364 if(bitslip_thr
== 0x7fffffff)
366 bitslip_thr
= bitslip_thr
/2;
368 printf("Read bitslip: ");
369 for(i
=DFII_PIX_DATA_SIZE
/2-1;i
>=0;i
--)
370 if(delay
[i
] > bitslip_thr
) {
377 static int read_level_scan(int silent
)
380 unsigned char prs
[DFII_NPHASES
*DFII_PIX_DATA_SIZE
];
385 printf("Read delays scan:\n");
387 /* Generate pseudo-random sequence */
389 for(i
=0;i
<DFII_NPHASES
*DFII_PIX_DATA_SIZE
;i
++) {
390 prv
= 1664525*prv
+ 1013904223;
395 sdram_dfii_pi0_address_write(0);
396 sdram_dfii_pi0_baddress_write(0);
397 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CS
);
400 /* Write test pattern */
401 for(p
=0;p
<DFII_NPHASES
;p
++)
402 for(i
=0;i
<DFII_PIX_DATA_SIZE
;i
++)
403 MMPTR(sdram_dfii_pix_wrdata_addr
[p
]+4*i
) = prs
[DFII_PIX_DATA_SIZE
*p
+i
];
404 sdram_dfii_piwr_address_write(0);
405 sdram_dfii_piwr_baddress_write(0);
406 command_pwr(DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
|DFII_COMMAND_WRDATA
);
408 /* Calibrate each DQ in turn */
409 sdram_dfii_pird_address_write(0);
410 sdram_dfii_pird_baddress_write(0);
412 for(i
=DFII_PIX_DATA_SIZE
/2-1;i
>=0;i
--) {
414 printf("m%d: ", (DFII_PIX_DATA_SIZE
/2-i
-1));
415 ddrphy_dly_sel_write(1 << (DFII_PIX_DATA_SIZE
/2-i
-1));
416 ddrphy_rdly_dq_rst_write(1);
417 for(j
=0; j
<ERR_DDRPHY_DELAY
;j
++) {
419 command_prd(DFII_COMMAND_CAS
|DFII_COMMAND_CS
|DFII_COMMAND_RDDATA
);
422 for(p
=0;p
<DFII_NPHASES
;p
++) {
423 if(MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*i
) != prs
[DFII_PIX_DATA_SIZE
*p
+i
])
425 if(MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*(i
+DFII_PIX_DATA_SIZE
/2)) != prs
[DFII_PIX_DATA_SIZE
*p
+i
+DFII_PIX_DATA_SIZE
/2])
429 printf("%d", working
);
431 ddrphy_rdly_dq_inc_write(1);
438 sdram_dfii_pi0_address_write(0);
439 sdram_dfii_pi0_baddress_write(0);
440 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
446 static void read_level(void)
449 unsigned char prs
[DFII_NPHASES
*DFII_PIX_DATA_SIZE
];
452 int delay
, delay_min
, delay_max
;
454 printf("Read delays: ");
456 /* Generate pseudo-random sequence */
458 for(i
=0;i
<DFII_NPHASES
*DFII_PIX_DATA_SIZE
;i
++) {
459 prv
= 1664525*prv
+ 1013904223;
464 sdram_dfii_pi0_address_write(0);
465 sdram_dfii_pi0_baddress_write(0);
466 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CS
);
469 /* Write test pattern */
470 for(p
=0;p
<DFII_NPHASES
;p
++)
471 for(i
=0;i
<DFII_PIX_DATA_SIZE
;i
++)
472 MMPTR(sdram_dfii_pix_wrdata_addr
[p
]+4*i
) = prs
[DFII_PIX_DATA_SIZE
*p
+i
];
473 sdram_dfii_piwr_address_write(0);
474 sdram_dfii_piwr_baddress_write(0);
475 command_pwr(DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
|DFII_COMMAND_WRDATA
);
477 /* Calibrate each DQ in turn */
478 sdram_dfii_pird_address_write(0);
479 sdram_dfii_pird_baddress_write(0);
480 for(i
=0;i
<DFII_PIX_DATA_SIZE
/2;i
++) {
481 ddrphy_dly_sel_write(1 << (DFII_PIX_DATA_SIZE
/2-i
-1));
484 /* Find smallest working delay */
485 ddrphy_rdly_dq_rst_write(1);
487 command_prd(DFII_COMMAND_CAS
|DFII_COMMAND_CS
|DFII_COMMAND_RDDATA
);
490 for(p
=0;p
<DFII_NPHASES
;p
++) {
491 if(MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*i
) != prs
[DFII_PIX_DATA_SIZE
*p
+i
])
493 if(MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*(i
+DFII_PIX_DATA_SIZE
/2)) != prs
[DFII_PIX_DATA_SIZE
*p
+i
+DFII_PIX_DATA_SIZE
/2])
499 if(delay
>= ERR_DDRPHY_DELAY
)
501 ddrphy_rdly_dq_inc_write(1);
505 /* Get a bit further into the working zone */
509 ddrphy_rdly_dq_inc_write(1);
513 ddrphy_rdly_dq_inc_write(1);
516 /* Find largest working delay */
518 command_prd(DFII_COMMAND_CAS
|DFII_COMMAND_CS
|DFII_COMMAND_RDDATA
);
521 for(p
=0;p
<DFII_NPHASES
;p
++) {
522 if(MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*i
) != prs
[DFII_PIX_DATA_SIZE
*p
+i
])
524 if(MMPTR(sdram_dfii_pix_rddata_addr
[p
]+4*(i
+DFII_PIX_DATA_SIZE
/2)) != prs
[DFII_PIX_DATA_SIZE
*p
+i
+DFII_PIX_DATA_SIZE
/2])
530 if(delay
>= ERR_DDRPHY_DELAY
)
532 ddrphy_rdly_dq_inc_write(1);
536 printf("%d:%02d-%02d ", DFII_PIX_DATA_SIZE
/2-i
-1, delay_min
, delay_max
);
538 /* Set delay to the middle */
539 ddrphy_rdly_dq_rst_write(1);
540 for(j
=0;j
<(delay_min
+delay_max
)/2;j
++)
541 ddrphy_rdly_dq_inc_write(1);
545 sdram_dfii_pi0_address_write(0);
546 sdram_dfii_pi0_baddress_write(0);
547 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
550 printf("completed\n");
552 #endif /* CSR_DDRPHY_BASE */
554 static unsigned int seed_to_data_32(unsigned int seed
, int random
)
557 return 1664525*seed
+ 1013904223;
562 static unsigned short seed_to_data_16(unsigned short seed
, int random
)
565 return 25173*seed
+ 13849;
570 #define ONEZERO 0xAAAAAAAA
571 #define ZEROONE 0x55555555
573 #ifndef MEMTEST_BUS_SIZE
574 #define MEMTEST_BUS_SIZE (512)
577 //#define MEMTEST_BUS_DEBUG
579 static int memtest_bus(void)
581 volatile unsigned int *array
= (unsigned int *)MAIN_RAM_BASE
;
587 for(i
=0;i
<MEMTEST_BUS_SIZE
/4;i
++) {
592 for(i
=0;i
<MEMTEST_BUS_SIZE
/4;i
++) {
594 if(rdata
!= ONEZERO
) {
596 #ifdef MEMTEST_BUS_DEBUG
597 printf("[bus: %0x]: %08x vs %08x\n", i
, rdata
, ONEZERO
);
602 for(i
=0;i
<MEMTEST_BUS_SIZE
/4;i
++) {
607 for(i
=0;i
<MEMTEST_BUS_SIZE
/4;i
++) {
609 if(rdata
!= ZEROONE
) {
611 #ifdef MEMTEST_BUS_DEBUG
612 printf("[bus %0x]: %08x vs %08x\n", i
, rdata
, ZEROONE
);
620 #ifndef MEMTEST_DATA_SIZE
621 #define MEMTEST_DATA_SIZE (2*1024*1024)
623 #define MEMTEST_DATA_RANDOM 1
625 //#define MEMTEST_DATA_DEBUG
627 static int memtest_data(void)
629 volatile unsigned int *array
= (unsigned int *)MAIN_RAM_BASE
;
631 unsigned int seed_32
;
637 for(i
=0;i
<MEMTEST_DATA_SIZE
/4;i
++) {
638 seed_32
= seed_to_data_32(seed_32
, MEMTEST_DATA_RANDOM
);
645 for(i
=0;i
<MEMTEST_DATA_SIZE
/4;i
++) {
646 seed_32
= seed_to_data_32(seed_32
, MEMTEST_DATA_RANDOM
);
648 if(rdata
!= seed_32
) {
650 #ifdef MEMTEST_DATA_DEBUG
651 printf("[data %0x]: %08x vs %08x\n", i
, rdata
, seed_32
);
658 #ifndef MEMTEST_ADDR_SIZE
659 #define MEMTEST_ADDR_SIZE (32*1024)
661 #define MEMTEST_ADDR_RANDOM 0
663 //#define MEMTEST_ADDR_DEBUG
665 static int memtest_addr(void)
667 volatile unsigned int *array
= (unsigned int *)MAIN_RAM_BASE
;
669 unsigned short seed_16
;
670 unsigned short rdata
;
675 for(i
=0;i
<MEMTEST_ADDR_SIZE
/4;i
++) {
676 seed_16
= seed_to_data_16(seed_16
, MEMTEST_ADDR_RANDOM
);
677 array
[(unsigned int) seed_16
] = i
;
683 for(i
=0;i
<MEMTEST_ADDR_SIZE
/4;i
++) {
684 seed_16
= seed_to_data_16(seed_16
, MEMTEST_ADDR_RANDOM
);
685 rdata
= array
[(unsigned int) seed_16
];
688 #ifdef MEMTEST_ADDR_DEBUG
689 printf("[addr %0x]: %08x vs %08x\n", i
, rdata
, i
);
699 int bus_errors
, data_errors
, addr_errors
;
701 bus_errors
= memtest_bus();
703 printf("Memtest bus failed: %d/%d errors\n", bus_errors
, 2*128);
705 data_errors
= memtest_data();
707 printf("Memtest data failed: %d/%d errors\n", data_errors
, MEMTEST_DATA_SIZE
/4);
709 addr_errors
= memtest_addr();
711 printf("Memtest addr failed: %d/%d errors\n", addr_errors
, MEMTEST_ADDR_SIZE
/4);
713 if(bus_errors
+ data_errors
+ addr_errors
!= 0)
716 printf("Memtest OK\n");
721 #ifdef CSR_DDRPHY_BASE
722 int sdrlevel(int silent
)
724 int delay
[DFII_PIX_DATA_SIZE
/2];
725 int high_skew
[DFII_PIX_DATA_SIZE
/2];
734 for(i
=0; i
<DFII_PIX_DATA_SIZE
/2; i
++) {
735 ddrphy_dly_sel_write(1<<i
);
736 ddrphy_rdly_dq_rst_write(1);
737 ddrphy_rdly_dq_bitslip_rst_write(1);
740 #ifndef CSR_DDRPHY_WLEVEL_EN_ADDR
741 for(i
=0; i
<DFII_PIX_DATA_SIZE
/2; i
++) {
747 if(!write_level(delay
, high_skew
))
750 /* scan possible read windows */
753 for(bitslip
=0; bitslip
<ERR_DDRPHY_BITSLIP
; bitslip
++) {
755 printf("Read bitslip: %d\n", bitslip
);
757 score
= read_level_scan(silent
);
758 if (score
> best_score
) {
759 best_bitslip
= bitslip
;
763 if (bitslip
== ERR_DDRPHY_BITSLIP
-1)
765 /* increment bitslip */
766 for(i
=0; i
<DFII_PIX_DATA_SIZE
/2; i
++)
770 /* select best read window */
771 printf("Best read bitslip: %d\n", best_bitslip
);
772 for(i
=0; i
<DFII_PIX_DATA_SIZE
/2; i
++) {
773 ddrphy_dly_sel_write(1<<i
);
774 ddrphy_rdly_dq_bitslip_rst_write(1);
775 for (j
=0; j
<best_bitslip
; j
++)
779 /* show scan and do leveling */
789 printf("Initializing SDRAM...\n");
792 #ifdef CSR_DDRPHY_BASE
793 #if CSR_DDRPHY_EN_VTC_ADDR
794 ddrphy_en_vtc_write(0);
797 #if CSR_DDRPHY_EN_VTC_ADDR
798 ddrphy_en_vtc_write(1);
803 #ifdef CSR_DDRPHY_BASE