lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
  21    - EUR 250
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
  23    - EUR 1250
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  33  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  37    - EUR
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  41  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  42  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  43  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  46    - shared with cole
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  48    - EUR 50, shared with samuel 10%
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  50
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  53    - EUR 50, shared with samuel (EUR 350)
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  59    - EUR 200
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  62    - donated
  63    - parent #198
  64    - EUR 200
  65  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  66   - MultiCompUnit (and Function Units) proof
  67  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  68   - donated
  69   - parent #195
  70  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  71
  72 ## Completed but not yet submitted:
  73
  74 TO SORT
  75
  76 28feb2022
  77
  78  - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
  79    * EUR 1500 (shared with [[tplaten]])
  80  - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
  81    * EUR 1500 (shared with [[tplaten]])
  82  - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
  83    * EUR 1000 (shared with [[tplaten]])
  84  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
  85    * EUR 500 (shared with [[programmerjake]])
  86  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  87    * EUR 400 (shared with [[programmerjake]])
  88
  89 before that
  90
  91  - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
  92    - EUR 1600
  93    - EUR 800 shared with [[klehman]]
  94    - EUR 800 shared with [[lkcl]]
  95  - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
  96    - EUR 800
  97  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  98  - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
  99  - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
 100  - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
 101    - EUR 500
 102  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
 103  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
 104  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
 105  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
 106  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
 107
 108
 109  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 110    - EUR 150
 111    - donated
 112  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 113    - EUR 200
 114    - donated
 115  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 116    - EUR 150
 117    - donated
 118  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 119    - EUR 200
 120    - donated
 121  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
 122    - EUR 700
 123    - (lip6.fr donated)
 124  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 125    - (total EUR 400 25% donated by LIP6)
 126    - EUR 100 lkcl
 127  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
 128    - EUR 900
 129    - shared with [[lxo]]
 130  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 131    - EUR 1100
 132    - shared with lauri, jacob
 133  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 134    - EUR 1250
 135    - Shared 50% with Staf
 136  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 137    - EUR 300
 138    - Shared with Staf, cole
 139  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 140    - EUR 450
 141    - Shared with Staf
 142  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 143  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 144    - Project 2019-10-043 06dec2020 wishbone
 145    - EUR (TBD)
 146
 147 ### Project 2019-10-029 14mar2020 coriolis2
 148
 149  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 150    - (total EUR 100 shared 50% with staf)
 151    - EUR 50 lkcl
 152  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 153    - (total EUR 1500 shared 50% with LIP6)
 154    - EUR 750 lkcl
 155  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 156    - (total EUR 400 shared 75% with LIP6)
 157    - EUR 300 lkcl
 158
 159 ### Project 2019-02-012 06dec2020 Core
 160
 161  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 162    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 163  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 164    - EUR 750 donated
 165  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 166    - EUR 1500
 167
 168 ### Project 2019-10-043 06dec2020 wishbone
 169
 170  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 171    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 172  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 173    - EUR 200
 174  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 175    - EUR 100
 176  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 177    - EUR 200
 178  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 179    - EUR 100
 180  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 181    - EUR 200
 182  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 183    - EUR 450
 184  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 185    - EUR 100
 186  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 187    - EUR 200 donated
 188  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 189    - EUR 250 (share with cole)
 190
 191 ### Project 2019-10-032 06dec2020 proofs
 192
 193  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 194    - parent #195
 195    - EUR 400 donated
 196  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 197    - parent #195
 198    - EUR 300 donated
 199  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 200    - EUR 400 donated
 201    - parent #195
 202  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 203    - EUR 400 donated
 204    - parent #195
 205
 206 ## Submitted for NLNet RFP
 207
 208 submitted 2021-dec-09 but not confirmed paid
 209
 210  - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
 211    - EUR 300
 212  - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
 213    - EUR 250
 214  - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
 215  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
 216  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
 217    - EUR 800 shared between:
 218    - EUR 500 [[lkcl]]
 219    - EUR 300 [[tplaten]]
 220  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
 221    - EUR 5500 shared between:
 222    - EUR 3850 lkcl
 223    - EUR 1650 Others
 224  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
 225    - EUR 1600
 226  - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
 227    - EUR 600
 228  - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
 229    - EUR 500 shared between:
 230    - EUR 100 [[lkcl]]
 231    - EUR 325 dmitry
 232    - EUR 75 maciej
 233  - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
 234
 235
 236 ### Project 2019-02-012 04sep2020 Core
 237
 238  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 239    - EUR 2000 total, shared with florent.  EUR 1200
 240
 241 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 242
 243 ## Paid
 244
 245 donation from NLNet confirmed received:
 246
 247 ### coriolis2 2021-apr-04
 248
 249  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 250    - EUR 3000
 251    - shared with Staf 50%
 252
 253 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 254
 255  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 256     - EUR 2000, python POWER9 simulator
 257     - Shared 50% with [[mnolan]], EUR 1000
 258  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 259     - EUR 250, functions needed for simulator
 260     - Shared 20% with [[mnolan]], EUR 50
 261
 262 ### proofs 2019-10-032
 263
 264  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 265    - EUR 500 shared 20% samuel, EUR 100
 266  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 267    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 268  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 269    - EUR 400 shared 25% [[mnolan]] EUR 100
 270  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 271    - EUR 150
 272
 273 ### wishbone 2019-10-043
 274
 275  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 276    - EUR 500
 277  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 278     - EUR 300
 279  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 280     - EUR 250
 281  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 282    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 283  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 284    - EUR 300
 285  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 286    - EUR 400, 50% shared [[programmerjake]] EUR 200
 287  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 288    - EUR 750, 33% shared [[programmerjake]] EUR 250
 289  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 290    - EUR 200 50% shared, cole, EUR 100
 291  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 292    - EUR 200
 293  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 294    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 295  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 296    - EUR 150
 297  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 298    - EUR 400 shared 50% [[mnolan]] EUR 200
 299  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 300    - EUR 250 shared 40% [[mnolan]] EUR 100
 301  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 302    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 303  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 304    - EUR 300 shared 50% [[mnolan]] EUR 150
 305  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 306    - EUR 750
 307  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 308   - EUR 100
 309  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 310   - EUR 100
 311  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 312    - EUR 100
 313  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 314    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 315
 316 ### Project 2019-02-012 28-apr-2020
 317
 318  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 319    - 6600 scoreboard multi-read/write
 320    - EUR 600
 321  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 322    - Partitioned equals and greater than comparison
 323    - Shared 50% with [[mnolan]]
 324    - EUR 200 (each)
 325  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 326    - partitioned scalar/vector shift
 327    - Shared 50% with [[lkcl]]
 328    - EUR 350 (each)
 329
 330 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 331
 332  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 333     - auto-parser of POWER9
 334     - Shared 50% with [[mnolan]]
 335     - EUR 500 (each)
 336
 337 ### Project 2019-10-029 Date 14mar2020
 338
 339 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 340   - EUR 1200
 341
 342 ### Project 2019-02-012 Date 12mar2020
 343
 344 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 345 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 346 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 347 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 348
 349 ### Project 2019-02-012 Date 28jan2020
 350
 351 * admin tasks
 352 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 353