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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LDST cix
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LDST sign-extend
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
23 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
24 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
27 - shared with cole
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
29 - EUR 50, shared with samuel 10%
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
34 - EUR 50, shared with samuel (EUR 350)
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
40 - EUR 400 shared 25% [[mnolan]] EUR 100
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
42 - EUR 500 shared [[mnolan]] samuel, TBD split
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST cache-inhibit
45 - EUR 200
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
47 - EUR 250 (share with cole)
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
53
54 ## Completed but not yet submitted:
55
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
57 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
59 - EUR 200
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST sign-extend
61 - EUR 100
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
63 - EUR 200
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
65 - EUR 100
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
67 - EUR 200
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
69 - EUR 450
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
71 - EUR 100
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
73
74 donated:
75
76 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
77 - with [[lkcl]]
78 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
80 - functions needed for simulator
81 - Shared 90% with [[lkcl]]
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> parent #198
83 - Formal proof of decoder
84 - EUR 200
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> parent #195
86 - POWER9 ALU proof
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> parent #195
88 - POWER9 CR proof
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> parent #195
90 - POWER9 BRANCH proof
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> parent #195
92 - POWER9 LOGICAL proof
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> parent #195
94 - POWER9 ROTATE proof
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
96 - MultiCompUnit (and Function Units) proof
97
98 ## Submitted for NLNet RFP
99
100 submitted but not confirmed paid:
101
102 ### Project 2019-02-012 04sep2020 Core
103
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
105 - EUR 2000 total, shared with florent. EUR 1200
106
107 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
108
109 ## Paid
110
111 donation from NLNet confirmed received:
112
113 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
114
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
116 - EUR 2000, python POWER9 simulator
117 - Shared 50% with [[mnolan]], EUR 1000
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
119 - EUR 250, functions needed for simulator
120 - Shared 20% with [[mnolan]], EUR 50
121
122 #### proofs 2019-10-032
123
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
125 - EUR 500 shared 20% samuel, EUR 100
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
127 - EUR 300 shared 1/6 [[mnolan]] EUR 50
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
129 - EUR 400 shared 25% [[mnolan]] EUR 100
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
131 - EUR 150
132
133 ### wishbone 2019-10-043
134
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
136 - EUR 500
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
138 - EUR 300
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
140 - EUR 250
141 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
142 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
144 - EUR 300
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
146 - EUR 400, 50% shared [[programmerjake]] EUR 200
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
148 - EUR 750, 33% shared [[programmerjake]] EUR 250
149 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
150 - EUR 200 50% shared, cole, EUR 100
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
152 - EUR 200
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
154 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
156 - EUR 150
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
158 - EUR 400 shared 50% [[mnolan]] EUR 200
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
160 - EUR 250 shared 40% [[mnolan]] EUR 100
161 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
162 - EUR 300 shared 1/3 [[mnolan]] EUR 100
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
164 - EUR 300 shared 50% [[mnolan]] EUR 150
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
166 - EUR 750
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
168 - EUR 100
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
170 - EUR 100
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
172 - EUR 100
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
174 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
175
176 ### Project 2019-02-012 28-apr-2020
177
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
179 - 6600 scoreboard multi-read/write
180 - EUR 600
181 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
182 - Partitioned equals and greater than comparison
183 - Shared 50% with [[mnolan]]
184 - EUR 200 (each)
185 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
186 - partitioned scalar/vector shift
187 - Shared 50% with [[lkcl]]
188 - EUR 350 (each)
189
190 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
191
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
193 - auto-parser of POWER9
194 - Shared 50% with [[mnolan]]
195 - EUR 500 (each)
196
197 ### Project 2019-10-029 Date 14mar2020
198
199 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
200
201 ### Project 2019-02-012 Date 12mar2020
202
203 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
204 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
205 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
206 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
207
208 ### Project 2019-02-012 Date 28jan2020
209
210 * admin tasks
211 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
212