1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
38 - https://bugs.libre-soc.org/show_bug.cgi?id=575
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
47 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
48 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
53 - EUR 50, shared with samuel 10%
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
58 - EUR 50, shared with samuel (EUR 350)
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
71 - MultiCompUnit (and Function Units) proof
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
77 ## Completed but not yet submitted:
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
84 * EUR 1500 (shared with [[tplaten]])
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
86 * EUR 1500 (shared with [[tplaten]])
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
88 * EUR 1000 (shared with [[tplaten]])
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
90 * EUR 500 (shared with [[programmerjake]])
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
92 * EUR 400 (shared with [[programmerjake]])
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
98 - EUR 800 shared with [[klehman]]
99 - EUR 800 shared with [[lkcl]]
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
126 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
130 - (total EUR 400 25% donated by LIP6)
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
134 - shared with [[lxo]]
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
137 - shared with lauri, jacob
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
140 - Shared 50% with Staf
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
143 - Shared with Staf, cole
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
149 - Project 2019-10-043 06dec2020 wishbone
152 ### Project 2019-10-029 14mar2020 coriolis2
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
155 - (total EUR 100 shared 50% with staf)
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
158 - (total EUR 1500 shared 50% with LIP6)
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
161 - (total EUR 400 shared 75% with LIP6)
164 ### Project 2019-02-012 06dec2020 Core
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
167 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
168 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
173 ### Project 2019-10-043 06dec2020 wishbone
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
176 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
191 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
194 - EUR 250 (share with cole)
196 ### Project 2019-10-032 06dec2020 proofs
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
211 ## Submitted for NLNet RFP
213 submitted 2021-dec-09 but not confirmed paid
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
222 - EUR 800 shared between:
224 - EUR 300 [[tplaten]]
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
226 - EUR 5500 shared between:
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
234 - EUR 500 shared between:
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
241 ### Project 2019-02-012 04sep2020 Core
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
244 - EUR 2000 total, shared with florent. EUR 1200
246 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
250 donation from NLNet confirmed received:
252 ### coriolis2 2021-apr-04
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
256 - shared with Staf 50%
258 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
261 - EUR 2000, python POWER9 simulator
262 - Shared 50% with [[mnolan]], EUR 1000
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
264 - EUR 250, functions needed for simulator
265 - Shared 20% with [[mnolan]], EUR 50
267 ### proofs 2019-10-032
269 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
270 - EUR 500 shared 20% samuel, EUR 100
271 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
272 - EUR 300 shared 1/6 [[mnolan]] EUR 50
273 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
274 - EUR 400 shared 25% [[mnolan]] EUR 100
275 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
278 ### wishbone 2019-10-043
280 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
286 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
287 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
290 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
291 - EUR 400, 50% shared [[programmerjake]] EUR 200
292 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
293 - EUR 750, 33% shared [[programmerjake]] EUR 250
294 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
295 - EUR 200 50% shared, cole, EUR 100
296 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
298 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
299 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
300 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
302 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
303 - EUR 400 shared 50% [[mnolan]] EUR 200
304 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
305 - EUR 250 shared 40% [[mnolan]] EUR 100
306 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
307 - EUR 300 shared 1/3 [[mnolan]] EUR 100
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
309 - EUR 300 shared 50% [[mnolan]] EUR 150
310 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
312 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
314 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
316 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
318 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
319 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
321 ### Project 2019-02-012 28-apr-2020
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
324 - 6600 scoreboard multi-read/write
326 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
327 - Partitioned equals and greater than comparison
328 - Shared 50% with [[mnolan]]
330 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
331 - partitioned scalar/vector shift
332 - Shared 50% with [[lkcl]]
335 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
337 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
338 - auto-parser of POWER9
339 - Shared 50% with [[mnolan]]
342 ### Project 2019-10-029 Date 14mar2020
344 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
347 ### Project 2019-02-012 Date 12mar2020
349 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
350 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
351 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
352 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
354 ### Project 2019-02-012 Date 28jan2020
357 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>