1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=858>
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
47 - https://bugs.libre-soc.org/show_bug.cgi?id=575
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
56 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
57 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
62 - EUR 50, shared with samuel 10%
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
67 - EUR 50, shared with samuel (EUR 350)
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
80 - MultiCompUnit (and Function Units) proof
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
86 ## Completed but not yet submitted:
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
93 * EUR 1500 (shared with [[tplaten]])
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
95 * EUR 1500 (shared with [[tplaten]])
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
97 * EUR 1000 (shared with [[tplaten]])
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
99 * EUR 500 (shared with [[programmerjake]])
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
101 * EUR 400 (shared with [[programmerjake]])
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
107 - EUR 800 shared with [[klehman]]
108 - EUR 800 shared with [[lkcl]]
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
135 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
139 - (total EUR 400 25% donated by LIP6)
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
143 - shared with [[lxo]]
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
146 - shared with lauri, jacob
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
149 - Shared 50% with Staf
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
152 - Shared with Staf, cole
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
158 - Project 2019-10-043 06dec2020 wishbone
161 ### Project 2019-10-029 14mar2020 coriolis2
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
164 - (total EUR 100 shared 50% with staf)
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
167 - (total EUR 1500 shared 50% with LIP6)
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
170 - (total EUR 400 shared 75% with LIP6)
173 ### Project 2019-02-012 06dec2020 Core
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
176 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
177 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
182 ### Project 2019-10-043 06dec2020 wishbone
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
185 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
200 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
203 - EUR 250 (share with cole)
205 ### Project 2019-10-032 06dec2020 proofs
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
220 ## Submitted for NLNet RFP
222 submitted 2021-dec-09 but not confirmed paid
224 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
231 - EUR 800 shared between:
233 - EUR 300 [[tplaten]]
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
235 - EUR 5500 shared between:
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
243 - EUR 500 shared between:
247 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
250 ### Project 2019-02-012 04sep2020 Core
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
253 - EUR 2000 total, shared with florent. EUR 1200
255 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
259 donation from NLNet confirmed received:
261 ### coriolis2 2021-apr-04
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
265 - shared with Staf 50%
267 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
269 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
270 - EUR 2000, python POWER9 simulator
271 - Shared 50% with [[mnolan]], EUR 1000
272 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
273 - EUR 250, functions needed for simulator
274 - Shared 20% with [[mnolan]], EUR 50
276 ### proofs 2019-10-032
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
279 - EUR 500 shared 20% samuel, EUR 100
280 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
281 - EUR 300 shared 1/6 [[mnolan]] EUR 50
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
283 - EUR 400 shared 25% [[mnolan]] EUR 100
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
287 ### wishbone 2019-10-043
289 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
291 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
293 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
295 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
296 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
297 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
299 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
300 - EUR 400, 50% shared [[programmerjake]] EUR 200
301 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
302 - EUR 750, 33% shared [[programmerjake]] EUR 250
303 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
304 - EUR 200 50% shared, cole, EUR 100
305 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
307 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
308 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
311 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
312 - EUR 400 shared 50% [[mnolan]] EUR 200
313 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
314 - EUR 250 shared 40% [[mnolan]] EUR 100
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
316 - EUR 300 shared 1/3 [[mnolan]] EUR 100
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
318 - EUR 300 shared 50% [[mnolan]] EUR 150
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
328 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
330 ### Project 2019-02-012 28-apr-2020
332 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
333 - 6600 scoreboard multi-read/write
335 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
336 - Partitioned equals and greater than comparison
337 - Shared 50% with [[mnolan]]
339 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
340 - partitioned scalar/vector shift
341 - Shared 50% with [[lkcl]]
344 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
346 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
347 - auto-parser of POWER9
348 - Shared 50% with [[mnolan]]
351 ### Project 2019-10-029 Date 14mar2020
353 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
356 ### Project 2019-02-012 Date 12mar2020
358 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
359 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
360 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
361 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
363 ### Project 2019-02-012 Date 28jan2020
366 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>