1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
38 - https://bugs.libre-soc.org/show_bug.cgi?id=575
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
47 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
48 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
53 - EUR 50, shared with samuel 10%
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
58 - EUR 50, shared with samuel (EUR 350)
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
71 - MultiCompUnit (and Function Units) proof
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
77 ## Completed but not yet submitted:
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
80 - EUR 800 shared with [[klehman]]
81 - EUR 800 shared with [[lkcl]]
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
83 - EUR 500 shared between:
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
93 - EUR 800 shared between:
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
97 - EUR 5500 shared between:
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
125 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
129 - (total EUR 400 25% donated by LIP6)
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
133 - shared with [[lxo]]
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
136 - shared with lauri, jacob
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
139 - Shared 50% with Staf
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
142 - Shared with Staf, cole
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
149 - shared with Staf 50%
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
151 - Project 2019-10-043 06dec2020 wishbone
154 ### Project 2019-10-029 14mar2020 coriolis2
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
157 - (total EUR 100 shared 50% with staf)
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
160 - (total EUR 1500 shared 50% with LIP6)
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
163 - (total EUR 400 shared 75% with LIP6)
166 ### Project 2019-02-012 06dec2020 Core
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
169 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
170 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
175 ### Project 2019-10-043 06dec2020 wishbone
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
178 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
193 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
196 - EUR 250 (share with cole)
198 ### Project 2019-10-032 06dec2020 proofs
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
209 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
213 ## Submitted for NLNet RFP
215 submitted but not confirmed paid:
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
219 ### Project 2019-02-012 04sep2020 Core
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
222 - EUR 2000 total, shared with florent. EUR 1200
224 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
228 donation from NLNet confirmed received:
230 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
233 - EUR 2000, python POWER9 simulator
234 - Shared 50% with [[mnolan]], EUR 1000
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
236 - EUR 250, functions needed for simulator
237 - Shared 20% with [[mnolan]], EUR 50
239 ### proofs 2019-10-032
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
242 - EUR 500 shared 20% samuel, EUR 100
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
244 - EUR 300 shared 1/6 [[mnolan]] EUR 50
245 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
246 - EUR 400 shared 25% [[mnolan]] EUR 100
247 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
250 ### wishbone 2019-10-043
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
258 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
259 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
263 - EUR 400, 50% shared [[programmerjake]] EUR 200
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
265 - EUR 750, 33% shared [[programmerjake]] EUR 250
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
267 - EUR 200 50% shared, cole, EUR 100
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
270 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
271 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
272 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
274 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
275 - EUR 400 shared 50% [[mnolan]] EUR 200
276 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
277 - EUR 250 shared 40% [[mnolan]] EUR 100
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
279 - EUR 300 shared 1/3 [[mnolan]] EUR 100
280 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
281 - EUR 300 shared 50% [[mnolan]] EUR 150
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
286 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
290 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
291 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
293 ### Project 2019-02-012 28-apr-2020
295 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
296 - 6600 scoreboard multi-read/write
298 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
299 - Partitioned equals and greater than comparison
300 - Shared 50% with [[mnolan]]
302 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
303 - partitioned scalar/vector shift
304 - Shared 50% with [[lkcl]]
307 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
310 - auto-parser of POWER9
311 - Shared 50% with [[mnolan]]
314 ### Project 2019-10-029 Date 14mar2020
316 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
319 ### Project 2019-02-012 Date 12mar2020
321 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
322 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
323 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
324 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
326 ### Project 2019-02-012 Date 28jan2020
329 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>