4e39f533ed651c3a2c952f8419b71d0610b0618b
[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
16 - EUR 250
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
20 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
21 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
24 - shared with cole
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
26 - EUR 50, shared with samuel 10%
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
37 - EUR 400 shared 25% [[mnolan]] EUR 100
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
39 - EUR 500 shared [[mnolan]] samuel, TBD split
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST cache-inhibit
42 - EUR 200
43
44 ## Completed but not yet submitted:
45
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST sign-extend
47 - EUR 100
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
49 - EUR 200
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
51 - EUR 100
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
53 - EUR 200
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
55 - EUR 450
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
57
58 ## Submitted for NLNet RFP
59
60 submitted but not confirmed paid:
61
62 ### Project 2019-02-012 04sep2020 Core
63
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
65 - EUR 2000 total, shared with florent. EUR 1200
66
67 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
68
69 ## Paid
70
71 donation from NLNet confirmed received:
72
73 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
74
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
76 - EUR 2000, python POWER9 simulator
77 - Shared 50% with [[mnolan]], EUR 1000
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
79 - EUR 250, functions needed for simulator
80 - Shared 20% with [[mnolan]], EUR 50
81
82 #### proofs 2019-10-032
83
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
85 - EUR 500 shared 20% samuel, EUR 100
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
87 - EUR 300 shared 1/6 [[mnolan]] EUR 50
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
89 - EUR 400 shared 25% [[mnolan]] EUR 100
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
91 - EUR 150
92
93 ### wishbone 2019-10-043
94
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
96 - EUR 500
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
98 - EUR 300
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
100 - EUR 250
101 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
102 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
104 - EUR 300
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
106 - EUR 400, 50% shared [[programmerjake]] EUR 200
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
108 - EUR 750, 33% shared [[programmerjake]] EUR 250
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
110 - EUR 200 50% shared, cole, EUR 100
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
112 - EUR 200
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
114 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
116 - EUR 150
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
118 - EUR 400 shared 50% [[mnolan]] EUR 200
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
120 - EUR 250 shared 40% [[mnolan]] EUR 100
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
122 - EUR 300 shared 1/3 [[mnolan]] EUR 100
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
124 - EUR 300 shared 50% [[mnolan]] EUR 150
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
126 - EUR 750
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
128 - EUR 100
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
130 - EUR 100
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
132 - EUR 100
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
134 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
135
136 ### Project 2019-02-012 28-apr-2020
137
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
139 - 6600 scoreboard multi-read/write
140 - EUR 600
141 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
142 - Partitioned equals and greater than comparison
143 - Shared 50% with [[mnolan]]
144 - EUR 200 (each)
145 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
146 - partitioned scalar/vector shift
147 - Shared 50% with [[lkcl]]
148 - EUR 350 (each)
149
150 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
151
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
153 - auto-parser of POWER9
154 - Shared 50% with [[mnolan]]
155 - EUR 500 (each)
156
157 ### Project 2019-10-029 Date 14mar2020
158
159 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
160
161 ### Project 2019-02-012 Date 12mar2020
162
163 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
164 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
165 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
166 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
167
168 ### Project 2019-02-012 Date 28jan2020
169
170 * admin tasks
171 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
172