1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
10 move things along from one stage to the next
12 ## Currently working on
15 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
16 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
35 - EUR 400 shared 25% [[mnolan]] EUR 100
37 ## Completed but not yet submitted:
39 ### 2019-10P-046 19-aug-2020 NLNet 2019 Formal Standards OpenPOWER
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
42 - EUR 2000, python POWER9 simulator
43 - Shared 50% with [[mnolan]], EUR 1000
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
45 - EUR 250, functions needed for simulator
46 - Shared 20% with [[mnolan]], EUR 50
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
51 - EUR 500 shared 20% samuel, EUR 100
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
53 - EUR 500 shared [[mnolan]] samuel, TBD split
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
55 - EUR 300 shared 1/6 [[mnolan]] EUR 50
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
57 - EUR 400 shared 25% [[mnolan]] EUR 100
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
67 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
68 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
72 - EUR 400, 50% shared [[programmerjake]] EUR 200
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
74 - EUR 750, 33% shared [[programmerjake]] EUR 250
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
76 - EUR 200 50% shared, cole, EUR 100
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
80 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
84 - EUR 400 shared 50% [[mnolan]] EUR 200
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
86 - EUR 250 shared 40% [[mnolan]] EUR 100
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
88 - EUR 300 shared 1/3 [[mnolan]] EUR 100
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
90 - EUR 300 shared 50% [[mnolan]] EUR 150
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
100 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
104 ## Submitted for NLNet RFP
106 submitted but not confirmed paid:
108 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
112 donation from NLNet confirmed received:
114 ### Project 2019-02-012 28-apr-2020
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
117 - 6600 scoreboard multi-read/write
119 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
120 - Partitioned equals and greater than comparison
121 - Shared 50% with [[mnolan]]
123 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
124 - partitioned scalar/vector shift
125 - Shared 50% with [[lkcl]]
128 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
131 - auto-parser of POWER9
132 - Shared 50% with [[mnolan]]
135 ### Project 2019-10-029 Date 14mar2020
137 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
139 ### Project 2019-02-012 Date 12mar2020
141 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
142 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
143 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
144 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
146 ### Project 2019-02-012 Date 28jan2020
149 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>