1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
37 - https://bugs.libre-soc.org/show_bug.cgi?id=575
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
46 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
47 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
52 - EUR 50, shared with samuel 10%
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
57 - EUR 50, shared with samuel (EUR 350)
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
70 - MultiCompUnit (and Function Units) proof
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
76 ## Completed but not yet submitted:
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
79 - EUR 800 shared with [[klehman]]
80 - EUR 800 shared with [[lkcl]]
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
82 - EUR 500 shared between:
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
92 - EUR 800 shared between:
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
96 - EUR 5500 shared between:
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
124 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
128 - (total EUR 400 25% donated by LIP6)
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
132 - shared with [[lxo]]
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
135 - shared with lauri, jacob
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
138 - Shared 50% with Staf
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
141 - Shared with Staf, cole
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
148 - shared with Staf 50%
149 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
150 - Project 2019-10-043 06dec2020 wishbone
153 ### Project 2019-10-029 14mar2020 coriolis2
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
156 - (total EUR 100 shared 50% with staf)
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
159 - (total EUR 1500 shared 50% with LIP6)
161 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
162 - (total EUR 400 shared 75% with LIP6)
165 ### Project 2019-02-012 06dec2020 Core
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
168 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
169 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
174 ### Project 2019-10-043 06dec2020 wishbone
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
177 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
180 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
192 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
195 - EUR 250 (share with cole)
197 ### Project 2019-10-032 06dec2020 proofs
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
212 ## Submitted for NLNet RFP
214 submitted but not confirmed paid:
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
218 ### Project 2019-02-012 04sep2020 Core
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
221 - EUR 2000 total, shared with florent. EUR 1200
223 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
227 donation from NLNet confirmed received:
229 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
232 - EUR 2000, python POWER9 simulator
233 - Shared 50% with [[mnolan]], EUR 1000
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
235 - EUR 250, functions needed for simulator
236 - Shared 20% with [[mnolan]], EUR 50
238 ### proofs 2019-10-032
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
241 - EUR 500 shared 20% samuel, EUR 100
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
243 - EUR 300 shared 1/6 [[mnolan]] EUR 50
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
245 - EUR 400 shared 25% [[mnolan]] EUR 100
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
249 ### wishbone 2019-10-043
251 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
255 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
257 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
258 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
259 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
261 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
262 - EUR 400, 50% shared [[programmerjake]] EUR 200
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
264 - EUR 750, 33% shared [[programmerjake]] EUR 250
265 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
266 - EUR 200 50% shared, cole, EUR 100
267 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
269 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
270 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
271 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
273 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
274 - EUR 400 shared 50% [[mnolan]] EUR 200
275 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
276 - EUR 250 shared 40% [[mnolan]] EUR 100
277 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
278 - EUR 300 shared 1/3 [[mnolan]] EUR 100
279 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
280 - EUR 300 shared 50% [[mnolan]] EUR 150
281 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
283 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
285 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
287 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
289 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
290 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
292 ### Project 2019-02-012 28-apr-2020
294 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
295 - 6600 scoreboard multi-read/write
297 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
298 - Partitioned equals and greater than comparison
299 - Shared 50% with [[mnolan]]
301 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
302 - partitioned scalar/vector shift
303 - Shared 50% with [[lkcl]]
306 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
309 - auto-parser of POWER9
310 - Shared 50% with [[mnolan]]
313 ### Project 2019-10-029 Date 14mar2020
315 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
318 ### Project 2019-02-012 Date 12mar2020
320 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
321 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
322 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
323 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
325 ### Project 2019-02-012 Date 28jan2020
328 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>