1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
9 * <https://libre-soc.org/task_db/>
11 # Priority tasks to keep an eye on
13 * <https://bugs.libre-soc.org/show_bug.cgi?id=899> transcendentals sim EUR 4000
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=252> 3D simulator EUR 7000
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=198> nmutil/etc Formal Proofs
17 * <https://bugs.libre-soc.org/show_bug.cgi?id=236> Atomics, Jacob
19 * <https://bugs.libre-soc.org/show_bug.cgi?id=728> ISACaller, Dmitry
21 * <https://bugs.libre-soc.org/show_bug.cgi?id=871> Pack/Unpack
23 * <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
25 * <https://bugs.libre-soc.org/show_bug.cgi?id=231> Video opcodes Standard
31 move things along from one stage to the next
33 ## Currently working on
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
63 - EUR 1000 of 1250 shared
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
73 - https://bugs.libre-soc.org/show_bug.cgi?id=575
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
81 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
82 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
87 - EUR 50, shared with samuel 10%
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
92 - EUR 50, shared with samuel (EUR 350)
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
105 - MultiCompUnit (and Function Units) proof
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
111 ## Completed but not yet submitted:
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
118 * EUR 1500 (shared with [[tplaten]])
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
120 * EUR 1500 (shared with [[tplaten]])
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
122 * EUR 1000 (shared with [[tplaten]])
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
124 * EUR 500 (shared with [[programmerjake]])
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
126 * EUR 400 (shared with [[programmerjake]])
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
132 - EUR 800 shared with [[klehman]]
133 - EUR 800 shared with [[lkcl]]
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
160 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
164 - (total EUR 400 25% donated by LIP6)
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
168 - shared with [[lxo]]
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
171 - shared with lauri, jacob
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
174 - Shared 50% with Staf
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
177 - Shared with Staf, cole
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
183 - Project 2019-10-043 06dec2020 wishbone
186 ### Project 2019-10-029 14mar2020 coriolis2
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
189 - (total EUR 100 shared 50% with staf)
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
192 - (total EUR 1500 shared 50% with LIP6)
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
195 - (total EUR 400 shared 75% with LIP6)
198 ### Project 2019-02-012 06dec2020 Core
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
201 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
202 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
207 ### Project 2019-10-043 06dec2020 wishbone
209 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
210 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
225 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
228 - EUR 250 (share with cole)
230 ### Project 2019-10-032 06dec2020 proofs
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
245 ## Submitted for NLNet RFP
247 submitted 2021-dec-09 but not confirmed paid
249 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
251 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
255 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
256 - EUR 800 shared between:
258 - EUR 300 [[tplaten]]
259 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
260 - EUR 5500 shared between:
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
265 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
267 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
268 - EUR 500 shared between:
272 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
275 ### Project 2019-02-012 04sep2020 Core
277 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
278 - EUR 2000 total, shared with florent. EUR 1200
280 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
284 donation from NLNet confirmed received:
286 ### coriolis2 2021-apr-04
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
290 - shared with Staf 50%
292 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
294 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
295 - EUR 2000, python POWER9 simulator
296 - Shared 50% with [[mnolan]], EUR 1000
297 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
298 - EUR 250, functions needed for simulator
299 - Shared 20% with [[mnolan]], EUR 50
301 ### proofs 2019-10-032
303 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
304 - EUR 500 shared 20% samuel, EUR 100
305 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
306 - EUR 300 shared 1/6 [[mnolan]] EUR 50
307 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
308 - EUR 400 shared 25% [[mnolan]] EUR 100
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
312 ### wishbone 2019-10-043
314 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
316 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
318 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
320 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
321 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
322 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
324 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
325 - EUR 400, 50% shared [[programmerjake]] EUR 200
326 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
327 - EUR 750, 33% shared [[programmerjake]] EUR 250
328 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
329 - EUR 200 50% shared, cole, EUR 100
330 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
332 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
333 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
334 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
336 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
337 - EUR 400 shared 50% [[mnolan]] EUR 200
338 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
339 - EUR 250 shared 40% [[mnolan]] EUR 100
340 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
341 - EUR 300 shared 1/3 [[mnolan]] EUR 100
342 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
343 - EUR 300 shared 50% [[mnolan]] EUR 150
344 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
346 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
348 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
350 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
352 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
353 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
355 ### Project 2019-02-012 28-apr-2020
357 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
358 - 6600 scoreboard multi-read/write
360 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
361 - Partitioned equals and greater than comparison
362 - Shared 50% with [[mnolan]]
364 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
365 - partitioned scalar/vector shift
366 - Shared 50% with [[lkcl]]
369 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
371 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
372 - auto-parser of POWER9
373 - Shared 50% with [[mnolan]]
376 ### Project 2019-10-029 Date 14mar2020
378 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
381 ### Project 2019-02-012 Date 12mar2020
383 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
384 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
385 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
386 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
388 ### Project 2019-02-012 Date 28jan2020
391 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>