1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
28 - https://bugs.libre-soc.org/show_bug.cgi?id=575
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
37 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
38 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
43 - EUR 50, shared with samuel 10%
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
48 - EUR 50, shared with samuel (EUR 350)
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
61 - MultiCompUnit (and Function Units) proof
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
67 ## Completed but not yet submitted:
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
69 - EUR 500 shared between:
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
79 - EUR 800 shared between:
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
83 - EUR 5500 shared between:
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
111 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
115 - (total EUR 400 25% donated by LIP6)
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
119 - shared with [[lxo]]
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
122 - shared with lauri, jacob
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
125 - Shared 50% with Staf
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
128 - Shared with Staf, cole
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
135 - shared with Staf 50%
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
137 - Project 2019-10-043 06dec2020 wishbone
140 ### Project 2019-10-029 14mar2020 coriolis2
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
143 - (total EUR 100 shared 50% with staf)
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
146 - (total EUR 1500 shared 50% with LIP6)
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
149 - (total EUR 400 shared 75% with LIP6)
152 ### Project 2019-02-012 06dec2020 Core
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
155 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
156 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
161 ### Project 2019-10-043 06dec2020 wishbone
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
164 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
179 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
182 - EUR 250 (share with cole)
184 ### Project 2019-10-032 06dec2020 proofs
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
199 ## Submitted for NLNet RFP
201 submitted but not confirmed paid:
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
205 ### Project 2019-02-012 04sep2020 Core
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
208 - EUR 2000 total, shared with florent. EUR 1200
210 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
214 donation from NLNet confirmed received:
216 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
219 - EUR 2000, python POWER9 simulator
220 - Shared 50% with [[mnolan]], EUR 1000
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
222 - EUR 250, functions needed for simulator
223 - Shared 20% with [[mnolan]], EUR 50
225 ### proofs 2019-10-032
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
228 - EUR 500 shared 20% samuel, EUR 100
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
230 - EUR 300 shared 1/6 [[mnolan]] EUR 50
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
232 - EUR 400 shared 25% [[mnolan]] EUR 100
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
236 ### wishbone 2019-10-043
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
244 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
245 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
249 - EUR 400, 50% shared [[programmerjake]] EUR 200
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
251 - EUR 750, 33% shared [[programmerjake]] EUR 250
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
253 - EUR 200 50% shared, cole, EUR 100
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
257 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
261 - EUR 400 shared 50% [[mnolan]] EUR 200
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
263 - EUR 250 shared 40% [[mnolan]] EUR 100
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
265 - EUR 300 shared 1/3 [[mnolan]] EUR 100
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
267 - EUR 300 shared 50% [[mnolan]] EUR 150
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
270 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
272 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
274 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
276 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
277 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
279 ### Project 2019-02-012 28-apr-2020
281 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
282 - 6600 scoreboard multi-read/write
284 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
285 - Partitioned equals and greater than comparison
286 - Shared 50% with [[mnolan]]
288 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
289 - partitioned scalar/vector shift
290 - Shared 50% with [[lkcl]]
293 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
295 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
296 - auto-parser of POWER9
297 - Shared 50% with [[mnolan]]
300 ### Project 2019-10-029 Date 14mar2020
302 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
305 ### Project 2019-02-012 Date 12mar2020
307 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
308 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
309 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
310 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
312 ### Project 2019-02-012 Date 28jan2020
315 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>