1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Priority tasks to keep an eye on
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=195> Power ISA Formal Proof
18 * <https://bugs.libre-soc.org/show_bug.cgi?id=198> nmutil/etc Formal Proofs
20 * <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
23 ## Currently working on
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
53 - EUR 1000 of 1250 shared
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
63 - https://bugs.libre-soc.org/show_bug.cgi?id=575
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
71 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
72 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
77 - EUR 50, shared with samuel 10%
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
82 - EUR 50, shared with samuel (EUR 350)
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
95 - MultiCompUnit (and Function Units) proof
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
101 ## Completed but not yet submitted:
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
108 * EUR 1500 (shared with [[tplaten]])
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
110 * EUR 1500 (shared with [[tplaten]])
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
112 * EUR 1000 (shared with [[tplaten]])
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
114 * EUR 500 (shared with [[programmerjake]])
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
116 * EUR 400 (shared with [[programmerjake]])
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
122 - EUR 800 shared with [[klehman]]
123 - EUR 800 shared with [[lkcl]]
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
150 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
154 - (total EUR 400 25% donated by LIP6)
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
158 - shared with [[lxo]]
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
161 - shared with lauri, jacob
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
164 - Shared 50% with Staf
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
167 - Shared with Staf, cole
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
173 - Project 2019-10-043 06dec2020 wishbone
176 ### Project 2019-10-029 14mar2020 coriolis2
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
179 - (total EUR 100 shared 50% with staf)
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
182 - (total EUR 1500 shared 50% with LIP6)
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
185 - (total EUR 400 shared 75% with LIP6)
188 ### Project 2019-02-012 06dec2020 Core
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
191 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
192 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
197 ### Project 2019-10-043 06dec2020 wishbone
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
200 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
209 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
215 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
218 - EUR 250 (share with cole)
220 ### Project 2019-10-032 06dec2020 proofs
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
235 ## Submitted for NLNet RFP
237 submitted 2021-dec-09 but not confirmed paid
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
245 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
246 - EUR 800 shared between:
248 - EUR 300 [[tplaten]]
249 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
250 - EUR 5500 shared between:
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
255 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
257 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
258 - EUR 500 shared between:
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
265 ### Project 2019-02-012 04sep2020 Core
267 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
268 - EUR 2000 total, shared with florent. EUR 1200
270 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
274 donation from NLNet confirmed received:
276 ### coriolis2 2021-apr-04
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
280 - shared with Staf 50%
282 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
285 - EUR 2000, python POWER9 simulator
286 - Shared 50% with [[mnolan]], EUR 1000
287 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
288 - EUR 250, functions needed for simulator
289 - Shared 20% with [[mnolan]], EUR 50
291 ### proofs 2019-10-032
293 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
294 - EUR 500 shared 20% samuel, EUR 100
295 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
296 - EUR 300 shared 1/6 [[mnolan]] EUR 50
297 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
298 - EUR 400 shared 25% [[mnolan]] EUR 100
299 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
302 ### wishbone 2019-10-043
304 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
306 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
310 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
311 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
312 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
314 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
315 - EUR 400, 50% shared [[programmerjake]] EUR 200
316 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
317 - EUR 750, 33% shared [[programmerjake]] EUR 250
318 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
319 - EUR 200 50% shared, cole, EUR 100
320 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
322 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
323 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
324 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
326 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
327 - EUR 400 shared 50% [[mnolan]] EUR 200
328 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
329 - EUR 250 shared 40% [[mnolan]] EUR 100
330 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
331 - EUR 300 shared 1/3 [[mnolan]] EUR 100
332 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
333 - EUR 300 shared 50% [[mnolan]] EUR 150
334 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
336 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
338 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
340 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
342 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
343 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
345 ### Project 2019-02-012 28-apr-2020
347 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
348 - 6600 scoreboard multi-read/write
350 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
351 - Partitioned equals and greater than comparison
352 - Shared 50% with [[mnolan]]
354 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
355 - partitioned scalar/vector shift
356 - Shared 50% with [[lkcl]]
359 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
361 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
362 - auto-parser of POWER9
363 - Shared 50% with [[mnolan]]
366 ### Project 2019-10-029 Date 14mar2020
368 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
371 ### Project 2019-02-012 Date 12mar2020
373 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
374 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
375 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
376 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
378 ### Project 2019-02-012 Date 28jan2020
381 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>