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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
16 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
19 - shared with cole
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
35 - EUR 400 shared 25% [[mnolan]] EUR 100
36
37 ## Completed but not yet submitted:
38
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
40 - EUR 300
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
42 - EUR 250
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
44 - EUR 2000, python POWER9 simulator
45 - Shared 50% with [[mnolan]], EUR 1000
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
47 - EUR 250, functions needed for simulator
48 - Shared 20% with [[mnolan]], EUR 50
49 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
50 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
52 - EUR 300
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
54 - EUR 400, 50% shared [[programmerjake]] EUR 200
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
56 - EUR 750, 33% shared [[programmerjake]] EUR 250
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
58 - EUR 200 50% shared, cole, EUR 100
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
60 - EUR 200
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
62 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
64 - EUR 500 shared 20% samuel, EUR 100
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
66 - EUR 150
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
68 - EUR 400 shared 50% [[mnolan]] EUR 200
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
70 - EUR 500 shared [[mnolan]] samuel, TBD split
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
72 - EUR 250 shared 40% [[mnolan]] EUR 100
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
74 - EUR 300 shared 1/3 [[mnolan]] EUR 100
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
76 - EUR 300 shared 1/6 [[mnolan]] EUR 50
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
78 - EUR 300 shared 50% [[mnolan]] EUR 150
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
80 - EUR 400 shared 25% [[mnolan]] EUR 100
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
82 - EUR 150
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
84 - EUR 750
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
86 - EUR 100
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
88 - EUR 100
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
90 - EUR 100
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
92 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
94 - EUR 500
95
96 ## Submitted for NLNet RFP
97
98 submitted but not confirmed paid:
99
100 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
101
102 ## Paid
103
104 donation from NLNet confirmed received:
105
106 ### Project 2019-02-012 28-apr-2020
107
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
109 - 6600 scoreboard multi-read/write
110 - EUR 600
111 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
112 - Partitioned equals and greater than comparison
113 - Shared 50% with [[mnolan]]
114 - EUR 200 (each)
115 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
116 - partitioned scalar/vector shift
117 - Shared 50% with [[lkcl]]
118 - EUR 350 (each)
119
120 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
121
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
123 - auto-parser of POWER9
124 - Shared 50% with [[mnolan]]
125 - EUR 500 (each)
126
127 ### Project 2019-10-029 Date 14mar2020
128
129 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
130
131 ### Project 2019-02-012 Date 12mar2020
132
133 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
134 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
135 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
136 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
137
138 ### Project 2019-02-012 Date 28jan2020
139
140 * admin tasks
141 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
142