1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
32 - https://bugs.libre-soc.org/show_bug.cgi?id=575
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
41 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
42 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
47 - EUR 50, shared with samuel 10%
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
52 - EUR 50, shared with samuel (EUR 350)
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
65 - MultiCompUnit (and Function Units) proof
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
71 ## Completed but not yet submitted:
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
78 * EUR 1500 (shared with [[tplaten]])
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
80 * EUR 1500 (shared with [[tplaten]])
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
82 * EUR 1000 (shared with [[tplaten]])
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
84 * EUR 500 (shared with [[programmerjake]])
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
86 * EUR 400 (shared with [[programmerjake]])
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
92 - EUR 800 shared with [[klehman]]
93 - EUR 800 shared with [[lkcl]]
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
120 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
124 - (total EUR 400 25% donated by LIP6)
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
128 - shared with [[lxo]]
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
131 - shared with lauri, jacob
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
134 - Shared 50% with Staf
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
137 - Shared with Staf, cole
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
143 - Project 2019-10-043 06dec2020 wishbone
146 ### Project 2019-10-029 14mar2020 coriolis2
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
149 - (total EUR 100 shared 50% with staf)
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
152 - (total EUR 1500 shared 50% with LIP6)
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
155 - (total EUR 400 shared 75% with LIP6)
158 ### Project 2019-02-012 06dec2020 Core
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
161 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
162 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
167 ### Project 2019-10-043 06dec2020 wishbone
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
170 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
185 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
188 - EUR 250 (share with cole)
190 ### Project 2019-10-032 06dec2020 proofs
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
205 ## Submitted for NLNet RFP
207 submitted 2021-dec-09 but not confirmed paid
209 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
216 - EUR 800 shared between:
218 - EUR 300 [[tplaten]]
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
220 - EUR 5500 shared between:
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
228 - EUR 500 shared between:
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
235 ### Project 2019-02-012 04sep2020 Core
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
238 - EUR 2000 total, shared with florent. EUR 1200
240 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
244 donation from NLNet confirmed received:
246 ### coriolis2 2021-apr-04
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
250 - shared with Staf 50%
252 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
255 - EUR 2000, python POWER9 simulator
256 - Shared 50% with [[mnolan]], EUR 1000
257 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
258 - EUR 250, functions needed for simulator
259 - Shared 20% with [[mnolan]], EUR 50
261 ### proofs 2019-10-032
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
264 - EUR 500 shared 20% samuel, EUR 100
265 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
266 - EUR 300 shared 1/6 [[mnolan]] EUR 50
267 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
268 - EUR 400 shared 25% [[mnolan]] EUR 100
269 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
272 ### wishbone 2019-10-043
274 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
276 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
280 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
281 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
285 - EUR 400, 50% shared [[programmerjake]] EUR 200
286 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
287 - EUR 750, 33% shared [[programmerjake]] EUR 250
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
289 - EUR 200 50% shared, cole, EUR 100
290 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
292 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
293 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
294 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
296 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
297 - EUR 400 shared 50% [[mnolan]] EUR 200
298 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
299 - EUR 250 shared 40% [[mnolan]] EUR 100
300 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
301 - EUR 300 shared 1/3 [[mnolan]] EUR 100
302 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
303 - EUR 300 shared 50% [[mnolan]] EUR 150
304 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
306 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
310 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
312 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
313 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
315 ### Project 2019-02-012 28-apr-2020
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
318 - 6600 scoreboard multi-read/write
320 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
321 - Partitioned equals and greater than comparison
322 - Shared 50% with [[mnolan]]
324 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
325 - partitioned scalar/vector shift
326 - Shared 50% with [[lkcl]]
329 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
332 - auto-parser of POWER9
333 - Shared 50% with [[mnolan]]
336 ### Project 2019-10-029 Date 14mar2020
338 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
341 ### Project 2019-02-012 Date 12mar2020
343 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
344 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
345 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
346 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
348 ### Project 2019-02-012 Date 28jan2020
351 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>