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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - https://bugs.libre-soc.org/show_bug.cgi?id=575
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcodes
19 - EUR
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
29 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
30 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
33 - shared with cole
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
35 - EUR 50, shared with samuel 10%
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
40 - EUR 50, shared with samuel (EUR 350)
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
47 - EUR 200
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
54 - donated
55 - parent #198
56 - EUR 200
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
58 - MultiCompUnit (and Function Units) proof
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
60 - donated
61 - parent #195
62
63 ## Completed but not yet submitted:
64
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
66 - Project 2019-10-043 06dec2020 wishbone
67 - EUR 0 (TBD)
68
69 ### Project 2019-10-029 14mar2020 coriolis2
70
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
72 - (total EUR 100 shared 50% with staf)
73 - EUR 50 lkcl
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
75 - (total EUR 1500 shared 50% with LIP6)
76 - EUR 750 lkcl
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
78 - (total EUR 400 shared 75% with LIP6)
79 - EUR 300 lkcl
80
81 ### Project 2019-02-012 06dec2020 Core
82
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
84 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
85 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
86 - EUR 750 donated
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
88 - EUR 1500
89
90 ### Project 2019-10-043 06dec2020 wishbone
91
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
93 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
95 - EUR 200
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
97 - EUR 100
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
99 - EUR 200
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
101 - EUR 100
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
103 - EUR 200
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
105 - EUR 450
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
107 - EUR 100
108 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
109 - EUR 200 donated
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
111 - EUR 250 (share with cole)
112
113 ### Project 2019-10-032 06dec2020 proofs
114
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
116 - parent #195
117 - EUR 400 donated
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
119 - parent #195
120 - EUR 300 donated
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
122 - EUR 400 donated
123 - parent #195
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
125 - EUR 400 donated
126 - parent #195
127
128 ## Submitted for NLNet RFP
129
130 submitted but not confirmed paid:
131
132 ### Project 2019-02-012 04sep2020 Core
133
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
135 - EUR 2000 total, shared with florent. EUR 1200
136
137 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
138
139 ## Paid
140
141 donation from NLNet confirmed received:
142
143 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
144
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
146 - EUR 2000, python POWER9 simulator
147 - Shared 50% with [[mnolan]], EUR 1000
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
149 - EUR 250, functions needed for simulator
150 - Shared 20% with [[mnolan]], EUR 50
151
152 ### proofs 2019-10-032
153
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
155 - EUR 500 shared 20% samuel, EUR 100
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
157 - EUR 300 shared 1/6 [[mnolan]] EUR 50
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
159 - EUR 400 shared 25% [[mnolan]] EUR 100
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
161 - EUR 150
162
163 ### wishbone 2019-10-043
164
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
166 - EUR 500
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
168 - EUR 300
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
170 - EUR 250
171 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
172 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
174 - EUR 300
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
176 - EUR 400, 50% shared [[programmerjake]] EUR 200
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
178 - EUR 750, 33% shared [[programmerjake]] EUR 250
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
180 - EUR 200 50% shared, cole, EUR 100
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
182 - EUR 200
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
184 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
186 - EUR 150
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
188 - EUR 400 shared 50% [[mnolan]] EUR 200
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
190 - EUR 250 shared 40% [[mnolan]] EUR 100
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
192 - EUR 300 shared 1/3 [[mnolan]] EUR 100
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
194 - EUR 300 shared 50% [[mnolan]] EUR 150
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
196 - EUR 750
197 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
198 - EUR 100
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
200 - EUR 100
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
202 - EUR 100
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
204 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
205
206 ### Project 2019-02-012 28-apr-2020
207
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
209 - 6600 scoreboard multi-read/write
210 - EUR 600
211 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
212 - Partitioned equals and greater than comparison
213 - Shared 50% with [[mnolan]]
214 - EUR 200 (each)
215 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
216 - partitioned scalar/vector shift
217 - Shared 50% with [[lkcl]]
218 - EUR 350 (each)
219
220 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
221
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
223 - auto-parser of POWER9
224 - Shared 50% with [[mnolan]]
225 - EUR 500 (each)
226
227 ### Project 2019-10-029 Date 14mar2020
228
229 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
230 - EUR 1200
231
232 ### Project 2019-02-012 Date 12mar2020
233
234 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
235 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
236 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
237 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
238
239 ### Project 2019-02-012 Date 28jan2020
240
241 * admin tasks
242 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
243