1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
11 move things along from one stage to the next
13 ## Currently working on
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
25 - https://bugs.libre-soc.org/show_bug.cgi?id=575
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
38 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
39 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
44 - EUR 50, shared with samuel 10%
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
49 - EUR 50, shared with samuel (EUR 350)
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
67 - MultiCompUnit (and Function Units) proof
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
73 ## Completed but not yet submitted:
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
87 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
91 - (total EUR 400 25% donated by LIP6)
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
98 - shared with lauri, jacob
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
101 - Shared 50% with Staf
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
104 - Shared with Staf, cole
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
111 - shared with Staf 50%
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
113 - Project 2019-10-043 06dec2020 wishbone
116 ### Project 2019-10-029 14mar2020 coriolis2
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
119 - (total EUR 100 shared 50% with staf)
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
122 - (total EUR 1500 shared 50% with LIP6)
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
125 - (total EUR 400 shared 75% with LIP6)
128 ### Project 2019-02-012 06dec2020 Core
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
131 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
132 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
137 ### Project 2019-10-043 06dec2020 wishbone
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
140 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
149 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
155 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
158 - EUR 250 (share with cole)
160 ### Project 2019-10-032 06dec2020 proofs
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
175 ## Submitted for NLNet RFP
177 submitted but not confirmed paid:
179 ### Project 2019-02-012 04sep2020 Core
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
182 - EUR 2000 total, shared with florent. EUR 1200
184 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
188 donation from NLNet confirmed received:
190 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
193 - EUR 2000, python POWER9 simulator
194 - Shared 50% with [[mnolan]], EUR 1000
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
196 - EUR 250, functions needed for simulator
197 - Shared 20% with [[mnolan]], EUR 50
199 ### proofs 2019-10-032
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
202 - EUR 500 shared 20% samuel, EUR 100
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
204 - EUR 300 shared 1/6 [[mnolan]] EUR 50
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
206 - EUR 400 shared 25% [[mnolan]] EUR 100
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
210 ### wishbone 2019-10-043
212 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
218 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
219 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
223 - EUR 400, 50% shared [[programmerjake]] EUR 200
224 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
225 - EUR 750, 33% shared [[programmerjake]] EUR 250
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
227 - EUR 200 50% shared, cole, EUR 100
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
231 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
235 - EUR 400 shared 50% [[mnolan]] EUR 200
236 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
237 - EUR 250 shared 40% [[mnolan]] EUR 100
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
239 - EUR 300 shared 1/3 [[mnolan]] EUR 100
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
241 - EUR 300 shared 50% [[mnolan]] EUR 150
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
251 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
253 ### Project 2019-02-012 28-apr-2020
255 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
256 - 6600 scoreboard multi-read/write
258 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
259 - Partitioned equals and greater than comparison
260 - Shared 50% with [[mnolan]]
262 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
263 - partitioned scalar/vector shift
264 - Shared 50% with [[lkcl]]
267 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
269 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
270 - auto-parser of POWER9
271 - Shared 50% with [[mnolan]]
274 ### Project 2019-10-029 Date 14mar2020
276 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
279 ### Project 2019-02-012 Date 12mar2020
281 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
282 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
283 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
284 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
286 ### Project 2019-02-012 Date 28jan2020
289 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>