1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
9 * <https://libre-soc.org/task_db/>
11 # Priority tasks to keep an eye on
13 * <https://bugs.libre-soc.org/show_bug.cgi?id=898> binutils objdump EUR 2500
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=871> Pack/Unpack
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
18 * <https://bugs.libre-soc.org/show_bug.cgi?id=254> 12500 3D
22 move things along from one stage to the next
24 ## Currently working on
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
54 - EUR 1000 of 1250 shared
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
64 - https://bugs.libre-soc.org/show_bug.cgi?id=575
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
72 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
73 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
78 - EUR 50, shared with samuel 10%
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
83 - EUR 50, shared with samuel (EUR 350)
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
96 - MultiCompUnit (and Function Units) proof
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
102 ## Completed but not yet submitted:
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
109 * EUR 1500 (shared with [[tplaten]])
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
111 * EUR 1500 (shared with [[tplaten]])
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
113 * EUR 1000 (shared with [[tplaten]])
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
115 * EUR 500 (shared with [[programmerjake]])
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
117 * EUR 400 (shared with [[programmerjake]])
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
123 - EUR 800 shared with [[klehman]]
124 - EUR 800 shared with [[lkcl]]
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
151 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
155 - (total EUR 400 25% donated by LIP6)
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
159 - shared with [[lxo]]
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
162 - shared with lauri, jacob
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
165 - Shared 50% with Staf
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
168 - Shared with Staf, cole
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
174 - Project 2019-10-043 06dec2020 wishbone
177 ### Project 2019-10-029 14mar2020 coriolis2
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
180 - (total EUR 100 shared 50% with staf)
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
183 - (total EUR 1500 shared 50% with LIP6)
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
186 - (total EUR 400 shared 75% with LIP6)
189 ### Project 2019-02-012 06dec2020 Core
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
192 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
193 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
198 ### Project 2019-10-043 06dec2020 wishbone
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
201 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
212 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
216 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
219 - EUR 250 (share with cole)
221 ### Project 2019-10-032 06dec2020 proofs
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
236 ## Submitted for NLNet RFP
238 submitted 2021-dec-09 but not confirmed paid
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
245 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
247 - EUR 800 shared between:
249 - EUR 300 [[tplaten]]
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
251 - EUR 5500 shared between:
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
259 - EUR 500 shared between:
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
266 ### Project 2019-02-012 04sep2020 Core
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
269 - EUR 2000 total, shared with florent. EUR 1200
271 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
275 donation from NLNet confirmed received:
277 ### coriolis2 2021-apr-04
279 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
281 - shared with Staf 50%
283 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
285 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
286 - EUR 2000, python POWER9 simulator
287 - Shared 50% with [[mnolan]], EUR 1000
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
289 - EUR 250, functions needed for simulator
290 - Shared 20% with [[mnolan]], EUR 50
292 ### proofs 2019-10-032
294 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
295 - EUR 500 shared 20% samuel, EUR 100
296 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
297 - EUR 300 shared 1/6 [[mnolan]] EUR 50
298 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
299 - EUR 400 shared 25% [[mnolan]] EUR 100
300 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
303 ### wishbone 2019-10-043
305 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
307 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
311 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
312 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
313 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
316 - EUR 400, 50% shared [[programmerjake]] EUR 200
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
318 - EUR 750, 33% shared [[programmerjake]] EUR 250
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
320 - EUR 200 50% shared, cole, EUR 100
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
324 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
328 - EUR 400 shared 50% [[mnolan]] EUR 200
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
330 - EUR 250 shared 40% [[mnolan]] EUR 100
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
332 - EUR 300 shared 1/3 [[mnolan]] EUR 100
333 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
334 - EUR 300 shared 50% [[mnolan]] EUR 150
335 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
337 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
339 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
341 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
343 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
344 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
346 ### Project 2019-02-012 28-apr-2020
348 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
349 - 6600 scoreboard multi-read/write
351 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
352 - Partitioned equals and greater than comparison
353 - Shared 50% with [[mnolan]]
355 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
356 - partitioned scalar/vector shift
357 - Shared 50% with [[lkcl]]
360 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
362 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
363 - auto-parser of POWER9
364 - Shared 50% with [[mnolan]]
367 ### Project 2019-10-029 Date 14mar2020
369 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
372 ### Project 2019-02-012 Date 12mar2020
374 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
375 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
376 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
377 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
379 ### Project 2019-02-012 Date 28jan2020
382 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>