1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
11 move things along from one stage to the next
13 ## Currently working on
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
23 - https://bugs.libre-soc.org/show_bug.cgi?id=575
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
36 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
37 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
42 - EUR 50, shared with samuel 10%
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
47 - EUR 50, shared with samuel (EUR 350)
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
65 - MultiCompUnit (and Function Units) proof
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
71 ## Completed but not yet submitted:
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
85 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
89 - (total EUR 400 25% donated by LIP6)
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
96 - shared with lauri, jacob
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
99 - Shared 50% with Staf
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
102 - Shared with Staf, cole
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
109 - shared with Staf 50%
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
111 - Project 2019-10-043 06dec2020 wishbone
114 ### Project 2019-10-029 14mar2020 coriolis2
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
117 - (total EUR 100 shared 50% with staf)
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
120 - (total EUR 1500 shared 50% with LIP6)
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
123 - (total EUR 400 shared 75% with LIP6)
126 ### Project 2019-02-012 06dec2020 Core
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
129 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
130 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
135 ### Project 2019-10-043 06dec2020 wishbone
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
138 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
149 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
153 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
156 - EUR 250 (share with cole)
158 ### Project 2019-10-032 06dec2020 proofs
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
173 ## Submitted for NLNet RFP
175 submitted but not confirmed paid:
177 ### Project 2019-02-012 04sep2020 Core
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
180 - EUR 2000 total, shared with florent. EUR 1200
182 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
186 donation from NLNet confirmed received:
188 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
191 - EUR 2000, python POWER9 simulator
192 - Shared 50% with [[mnolan]], EUR 1000
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
194 - EUR 250, functions needed for simulator
195 - Shared 20% with [[mnolan]], EUR 50
197 ### proofs 2019-10-032
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
200 - EUR 500 shared 20% samuel, EUR 100
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
202 - EUR 300 shared 1/6 [[mnolan]] EUR 50
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
204 - EUR 400 shared 25% [[mnolan]] EUR 100
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
208 ### wishbone 2019-10-043
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
212 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
216 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
217 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
221 - EUR 400, 50% shared [[programmerjake]] EUR 200
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
223 - EUR 750, 33% shared [[programmerjake]] EUR 250
224 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
225 - EUR 200 50% shared, cole, EUR 100
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
229 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
233 - EUR 400 shared 50% [[mnolan]] EUR 200
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
235 - EUR 250 shared 40% [[mnolan]] EUR 100
236 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
237 - EUR 300 shared 1/3 [[mnolan]] EUR 100
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
239 - EUR 300 shared 50% [[mnolan]] EUR 150
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
249 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
251 ### Project 2019-02-012 28-apr-2020
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
254 - 6600 scoreboard multi-read/write
256 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
257 - Partitioned equals and greater than comparison
258 - Shared 50% with [[mnolan]]
260 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
261 - partitioned scalar/vector shift
262 - Shared 50% with [[lkcl]]
265 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
267 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
268 - auto-parser of POWER9
269 - Shared 50% with [[mnolan]]
272 ### Project 2019-10-029 Date 14mar2020
274 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
277 ### Project 2019-02-012 Date 12mar2020
279 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
280 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
281 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
282 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
284 ### Project 2019-02-012 Date 28jan2020
287 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>