1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
9 * <https://libre-soc.org/task_db/>
11 # Priority tasks to keep an eye on
13 * <https://bugs.libre-soc.org/show_bug.cgi?id=864> parallel prefix EUR 3000
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=899> transcendentals sim EUR 4000
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=252> 3D simulator EUR 7000
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=198> nmutil/etc Formal Proofs
18 * <https://bugs.libre-soc.org/show_bug.cgi?id=236> Atomics, Jacob
20 * <https://bugs.libre-soc.org/show_bug.cgi?id=728> ISACaller, Dmitry
22 * <https://bugs.libre-soc.org/show_bug.cgi?id=871> Pack/Unpack
24 * <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
26 * <https://bugs.libre-soc.org/show_bug.cgi?id=231> Video opcodes Standard
28 * <https://bugs.libre-soc.org/show_bug.cgi?id=906> de-data-classify
29 * <https://bugs.libre-soc.org/show_bug.cgi?id=650> IntFp spec
34 move things along from one stage to the next
36 ## Currently working on
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
66 - EUR 1000 of 1250 shared
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
76 - https://bugs.libre-soc.org/show_bug.cgi?id=575
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
84 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
85 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
90 - EUR 50, shared with samuel 10%
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
95 - EUR 50, shared with samuel (EUR 350)
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
108 - MultiCompUnit (and Function Units) proof
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
114 ## Completed but not yet submitted:
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
121 * EUR 1500 (shared with [[tplaten]])
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
123 * EUR 1500 (shared with [[tplaten]])
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
125 * EUR 1000 (shared with [[tplaten]])
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
127 * EUR 500 (shared with [[programmerjake]])
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
129 * EUR 400 (shared with [[programmerjake]])
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
135 - EUR 800 shared with [[klehman]]
136 - EUR 800 shared with [[lkcl]]
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
163 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
167 - (total EUR 400 25% donated by LIP6)
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
171 - shared with [[lxo]]
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
174 - shared with lauri, jacob
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
177 - Shared 50% with Staf
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
180 - Shared with Staf, cole
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
186 - Project 2019-10-043 06dec2020 wishbone
189 ### Project 2019-10-029 14mar2020 coriolis2
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
192 - (total EUR 100 shared 50% with staf)
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
195 - (total EUR 1500 shared 50% with LIP6)
197 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
198 - (total EUR 400 shared 75% with LIP6)
201 ### Project 2019-02-012 06dec2020 Core
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
204 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
205 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
210 ### Project 2019-10-043 06dec2020 wishbone
212 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
213 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
224 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
228 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
231 - EUR 250 (share with cole)
233 ### Project 2019-10-032 06dec2020 proofs
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
248 ## Submitted for NLNet RFP
250 submitted 2021-dec-09 but not confirmed paid
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
257 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
259 - EUR 800 shared between:
261 - EUR 300 [[tplaten]]
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
263 - EUR 5500 shared between:
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
270 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
271 - EUR 500 shared between:
275 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
278 ### Project 2019-02-012 04sep2020 Core
280 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
281 - EUR 2000 total, shared with florent. EUR 1200
283 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
287 donation from NLNet confirmed received:
289 ### coriolis2 2021-apr-04
291 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
293 - shared with Staf 50%
295 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
297 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
298 - EUR 2000, python POWER9 simulator
299 - Shared 50% with [[mnolan]], EUR 1000
300 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
301 - EUR 250, functions needed for simulator
302 - Shared 20% with [[mnolan]], EUR 50
304 ### proofs 2019-10-032
306 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
307 - EUR 500 shared 20% samuel, EUR 100
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
309 - EUR 300 shared 1/6 [[mnolan]] EUR 50
310 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
311 - EUR 400 shared 25% [[mnolan]] EUR 100
312 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
315 ### wishbone 2019-10-043
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
323 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
324 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
328 - EUR 400, 50% shared [[programmerjake]] EUR 200
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
330 - EUR 750, 33% shared [[programmerjake]] EUR 250
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
332 - EUR 200 50% shared, cole, EUR 100
333 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
335 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
336 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
337 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
339 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
340 - EUR 400 shared 50% [[mnolan]] EUR 200
341 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
342 - EUR 250 shared 40% [[mnolan]] EUR 100
343 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
344 - EUR 300 shared 1/3 [[mnolan]] EUR 100
345 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
346 - EUR 300 shared 50% [[mnolan]] EUR 150
347 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
349 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
351 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
353 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
355 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
356 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
358 ### Project 2019-02-012 28-apr-2020
360 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
361 - 6600 scoreboard multi-read/write
363 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
364 - Partitioned equals and greater than comparison
365 - Shared 50% with [[mnolan]]
367 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
368 - partitioned scalar/vector shift
369 - Shared 50% with [[lkcl]]
372 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
374 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
375 - auto-parser of POWER9
376 - Shared 50% with [[mnolan]]
379 ### Project 2019-10-029 Date 14mar2020
381 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
384 ### Project 2019-02-012 Date 12mar2020
386 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
387 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
388 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
389 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
391 ### Project 2019-02-012 Date 28jan2020
394 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>