1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
44 - EUR 1000 of 1250 shared
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
54 - https://bugs.libre-soc.org/show_bug.cgi?id=575
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
62 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
63 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
68 - EUR 50, shared with samuel 10%
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
73 - EUR 50, shared with samuel (EUR 350)
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
86 - MultiCompUnit (and Function Units) proof
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
92 ## Completed but not yet submitted:
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
99 * EUR 1500 (shared with [[tplaten]])
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
101 * EUR 1500 (shared with [[tplaten]])
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
103 * EUR 1000 (shared with [[tplaten]])
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
105 * EUR 500 (shared with [[programmerjake]])
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
107 * EUR 400 (shared with [[programmerjake]])
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
113 - EUR 800 shared with [[klehman]]
114 - EUR 800 shared with [[lkcl]]
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
141 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
145 - (total EUR 400 25% donated by LIP6)
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
149 - shared with [[lxo]]
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
152 - shared with lauri, jacob
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
155 - Shared 50% with Staf
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
158 - Shared with Staf, cole
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
164 - Project 2019-10-043 06dec2020 wishbone
167 ### Project 2019-10-029 14mar2020 coriolis2
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
170 - (total EUR 100 shared 50% with staf)
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
173 - (total EUR 1500 shared 50% with LIP6)
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
176 - (total EUR 400 shared 75% with LIP6)
179 ### Project 2019-02-012 06dec2020 Core
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
182 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
183 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
188 ### Project 2019-10-043 06dec2020 wishbone
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
191 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
206 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
209 - EUR 250 (share with cole)
211 ### Project 2019-10-032 06dec2020 proofs
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
226 ## Submitted for NLNet RFP
228 submitted 2021-dec-09 but not confirmed paid
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
236 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
237 - EUR 800 shared between:
239 - EUR 300 [[tplaten]]
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
241 - EUR 5500 shared between:
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
249 - EUR 500 shared between:
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
256 ### Project 2019-02-012 04sep2020 Core
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
259 - EUR 2000 total, shared with florent. EUR 1200
261 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
265 donation from NLNet confirmed received:
267 ### coriolis2 2021-apr-04
269 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
271 - shared with Staf 50%
273 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
275 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
276 - EUR 2000, python POWER9 simulator
277 - Shared 50% with [[mnolan]], EUR 1000
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
279 - EUR 250, functions needed for simulator
280 - Shared 20% with [[mnolan]], EUR 50
282 ### proofs 2019-10-032
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
285 - EUR 500 shared 20% samuel, EUR 100
286 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
287 - EUR 300 shared 1/6 [[mnolan]] EUR 50
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
289 - EUR 400 shared 25% [[mnolan]] EUR 100
290 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
293 ### wishbone 2019-10-043
295 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
297 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
299 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
301 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
302 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
303 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
305 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
306 - EUR 400, 50% shared [[programmerjake]] EUR 200
307 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
308 - EUR 750, 33% shared [[programmerjake]] EUR 250
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
310 - EUR 200 50% shared, cole, EUR 100
311 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
313 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
314 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
318 - EUR 400 shared 50% [[mnolan]] EUR 200
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
320 - EUR 250 shared 40% [[mnolan]] EUR 100
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
322 - EUR 300 shared 1/3 [[mnolan]] EUR 100
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
324 - EUR 300 shared 50% [[mnolan]] EUR 150
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
333 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
334 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
336 ### Project 2019-02-012 28-apr-2020
338 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
339 - 6600 scoreboard multi-read/write
341 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
342 - Partitioned equals and greater than comparison
343 - Shared 50% with [[mnolan]]
345 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
346 - partitioned scalar/vector shift
347 - Shared 50% with [[lkcl]]
350 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
352 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
353 - auto-parser of POWER9
354 - Shared 50% with [[mnolan]]
357 ### Project 2019-10-029 Date 14mar2020
359 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
362 ### Project 2019-02-012 Date 12mar2020
364 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
365 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
366 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
367 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
369 ### Project 2019-02-012 Date 28jan2020
372 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>