1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
9 * <https://libre-soc.org/task_db/>
11 # Priority tasks to keep an eye on
13 * <https://bugs.libre-soc.org/show_bug.cgi?id=899> transcendentals sim EUR 4000
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=252> 3D simulator EUR 7000
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=198> nmutil/etc Formal Proofs
17 * <https://bugs.libre-soc.org/show_bug.cgi?id=236> Atomics, Jacob
19 * <https://bugs.libre-soc.org/show_bug.cgi?id=728> ISACaller, Dmitry
21 * <https://bugs.libre-soc.org/show_bug.cgi?id=871> Pack/Unpack
23 * <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
25 * <https://bugs.libre-soc.org/show_bug.cgi?id=231> Video opcodes Standard
27 * <https://bugs.libre-soc.org/show_bug.cgi?id=906> de-data-classify
32 move things along from one stage to the next
34 ## Currently working on
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
64 - EUR 1000 of 1250 shared
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
74 - https://bugs.libre-soc.org/show_bug.cgi?id=575
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
82 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
83 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
88 - EUR 50, shared with samuel 10%
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
93 - EUR 50, shared with samuel (EUR 350)
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
106 - MultiCompUnit (and Function Units) proof
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
112 ## Completed but not yet submitted:
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
119 * EUR 1500 (shared with [[tplaten]])
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
121 * EUR 1500 (shared with [[tplaten]])
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
123 * EUR 1000 (shared with [[tplaten]])
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
125 * EUR 500 (shared with [[programmerjake]])
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
127 * EUR 400 (shared with [[programmerjake]])
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
133 - EUR 800 shared with [[klehman]]
134 - EUR 800 shared with [[lkcl]]
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
149 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
161 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
165 - (total EUR 400 25% donated by LIP6)
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
169 - shared with [[lxo]]
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
172 - shared with lauri, jacob
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
175 - Shared 50% with Staf
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
178 - Shared with Staf, cole
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
184 - Project 2019-10-043 06dec2020 wishbone
187 ### Project 2019-10-029 14mar2020 coriolis2
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
190 - (total EUR 100 shared 50% with staf)
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
193 - (total EUR 1500 shared 50% with LIP6)
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
196 - (total EUR 400 shared 75% with LIP6)
199 ### Project 2019-02-012 06dec2020 Core
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
202 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
203 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
208 ### Project 2019-10-043 06dec2020 wishbone
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
211 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
212 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
224 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
226 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
229 - EUR 250 (share with cole)
231 ### Project 2019-10-032 06dec2020 proofs
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
236 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
246 ## Submitted for NLNet RFP
248 submitted 2021-dec-09 but not confirmed paid
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
255 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
257 - EUR 800 shared between:
259 - EUR 300 [[tplaten]]
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
261 - EUR 5500 shared between:
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
269 - EUR 500 shared between:
273 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
276 ### Project 2019-02-012 04sep2020 Core
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
279 - EUR 2000 total, shared with florent. EUR 1200
281 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
285 donation from NLNet confirmed received:
287 ### coriolis2 2021-apr-04
289 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
291 - shared with Staf 50%
293 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
295 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
296 - EUR 2000, python POWER9 simulator
297 - Shared 50% with [[mnolan]], EUR 1000
298 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
299 - EUR 250, functions needed for simulator
300 - Shared 20% with [[mnolan]], EUR 50
302 ### proofs 2019-10-032
304 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
305 - EUR 500 shared 20% samuel, EUR 100
306 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
307 - EUR 300 shared 1/6 [[mnolan]] EUR 50
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
309 - EUR 400 shared 25% [[mnolan]] EUR 100
310 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
313 ### wishbone 2019-10-043
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
321 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
322 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
326 - EUR 400, 50% shared [[programmerjake]] EUR 200
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
328 - EUR 750, 33% shared [[programmerjake]] EUR 250
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
330 - EUR 200 50% shared, cole, EUR 100
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
333 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
334 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
335 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
337 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
338 - EUR 400 shared 50% [[mnolan]] EUR 200
339 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
340 - EUR 250 shared 40% [[mnolan]] EUR 100
341 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
342 - EUR 300 shared 1/3 [[mnolan]] EUR 100
343 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
344 - EUR 300 shared 50% [[mnolan]] EUR 150
345 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
347 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
349 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
351 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
353 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
354 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
356 ### Project 2019-02-012 28-apr-2020
358 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
359 - 6600 scoreboard multi-read/write
361 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
362 - Partitioned equals and greater than comparison
363 - Shared 50% with [[mnolan]]
365 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
366 - partitioned scalar/vector shift
367 - Shared 50% with [[lkcl]]
370 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
372 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
373 - auto-parser of POWER9
374 - Shared 50% with [[mnolan]]
377 ### Project 2019-10-029 Date 14mar2020
379 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
382 ### Project 2019-02-012 Date 12mar2020
384 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
385 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
386 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
387 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
389 ### Project 2019-02-012 Date 28jan2020
392 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>