1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
9 * <https://libre-soc.org/task_db/>
11 # Priority tasks to keep an eye on
13 * <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
18 move things along from one stage to the next
20 ## Currently working on
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
50 - EUR 1000 of 1250 shared
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
60 - https://bugs.libre-soc.org/show_bug.cgi?id=575
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
68 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
69 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
74 - EUR 50, shared with samuel 10%
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
79 - EUR 50, shared with samuel (EUR 350)
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
92 - MultiCompUnit (and Function Units) proof
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
98 ## Completed but not yet submitted:
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
105 * EUR 1500 (shared with [[tplaten]])
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
107 * EUR 1500 (shared with [[tplaten]])
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
109 * EUR 1000 (shared with [[tplaten]])
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
111 * EUR 500 (shared with [[programmerjake]])
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
113 * EUR 400 (shared with [[programmerjake]])
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
119 - EUR 800 shared with [[klehman]]
120 - EUR 800 shared with [[lkcl]]
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
147 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
151 - (total EUR 400 25% donated by LIP6)
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
155 - shared with [[lxo]]
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
158 - shared with lauri, jacob
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
161 - Shared 50% with Staf
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
164 - Shared with Staf, cole
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
170 - Project 2019-10-043 06dec2020 wishbone
173 ### Project 2019-10-029 14mar2020 coriolis2
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
176 - (total EUR 100 shared 50% with staf)
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
179 - (total EUR 1500 shared 50% with LIP6)
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
182 - (total EUR 400 shared 75% with LIP6)
185 ### Project 2019-02-012 06dec2020 Core
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
188 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
189 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
194 ### Project 2019-10-043 06dec2020 wishbone
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
197 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
212 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
215 - EUR 250 (share with cole)
217 ### Project 2019-10-032 06dec2020 proofs
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
232 ## Submitted for NLNet RFP
234 submitted 2021-dec-09 but not confirmed paid
236 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
243 - EUR 800 shared between:
245 - EUR 300 [[tplaten]]
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
247 - EUR 5500 shared between:
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
255 - EUR 500 shared between:
259 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
262 ### Project 2019-02-012 04sep2020 Core
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
265 - EUR 2000 total, shared with florent. EUR 1200
267 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
271 donation from NLNet confirmed received:
273 ### coriolis2 2021-apr-04
275 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
277 - shared with Staf 50%
279 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
281 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
282 - EUR 2000, python POWER9 simulator
283 - Shared 50% with [[mnolan]], EUR 1000
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
285 - EUR 250, functions needed for simulator
286 - Shared 20% with [[mnolan]], EUR 50
288 ### proofs 2019-10-032
290 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
291 - EUR 500 shared 20% samuel, EUR 100
292 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
293 - EUR 300 shared 1/6 [[mnolan]] EUR 50
294 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
295 - EUR 400 shared 25% [[mnolan]] EUR 100
296 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
299 ### wishbone 2019-10-043
301 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
303 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
305 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
307 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
308 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
311 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
312 - EUR 400, 50% shared [[programmerjake]] EUR 200
313 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
314 - EUR 750, 33% shared [[programmerjake]] EUR 250
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
316 - EUR 200 50% shared, cole, EUR 100
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
320 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
324 - EUR 400 shared 50% [[mnolan]] EUR 200
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
326 - EUR 250 shared 40% [[mnolan]] EUR 100
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
328 - EUR 300 shared 1/3 [[mnolan]] EUR 100
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
330 - EUR 300 shared 50% [[mnolan]] EUR 150
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
333 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
335 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
337 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
339 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
340 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
342 ### Project 2019-02-012 28-apr-2020
344 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
345 - 6600 scoreboard multi-read/write
347 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
348 - Partitioned equals and greater than comparison
349 - Shared 50% with [[mnolan]]
351 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
352 - partitioned scalar/vector shift
353 - Shared 50% with [[lkcl]]
356 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
358 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
359 - auto-parser of POWER9
360 - Shared 50% with [[mnolan]]
363 ### Project 2019-10-029 Date 14mar2020
365 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
368 ### Project 2019-02-012 Date 12mar2020
370 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
371 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
372 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
373 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
375 ### Project 2019-02-012 Date 28jan2020
378 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>