1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
10 move things along from one stage to the next
12 ## Currently working on
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
18 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
19 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
24 - EUR 50, shared with samuel 10%
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
29 - EUR 50, shared with samuel (EUR 350)
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
35 - EUR 400 shared 25% [[mnolan]] EUR 100
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
37 - EUR 500 shared [[mnolan]] samuel, TBD split
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST cache-inhibit
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
42 - EUR 250 (share with cole)
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
49 ## Completed but not yet submitted:
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
52 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST sign-extend
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
71 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
73 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
75 - functions needed for simulator
76 - Shared 90% with [[lkcl]]
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> parent #198
78 - Formal proof of decoder
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> parent #195
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> parent #195
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> parent #195
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> parent #195
87 - POWER9 LOGICAL proof
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> parent #195
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
91 - MultiCompUnit (and Function Units) proof
93 ## Submitted for NLNet RFP
95 submitted but not confirmed paid:
97 ### Project 2019-02-012 04sep2020 Core
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
100 - EUR 2000 total, shared with florent. EUR 1200
102 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
106 donation from NLNet confirmed received:
108 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
111 - EUR 2000, python POWER9 simulator
112 - Shared 50% with [[mnolan]], EUR 1000
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
114 - EUR 250, functions needed for simulator
115 - Shared 20% with [[mnolan]], EUR 50
117 #### proofs 2019-10-032
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
120 - EUR 500 shared 20% samuel, EUR 100
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
122 - EUR 300 shared 1/6 [[mnolan]] EUR 50
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
124 - EUR 400 shared 25% [[mnolan]] EUR 100
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
128 ### wishbone 2019-10-043
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
136 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
137 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
141 - EUR 400, 50% shared [[programmerjake]] EUR 200
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
143 - EUR 750, 33% shared [[programmerjake]] EUR 250
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
145 - EUR 200 50% shared, cole, EUR 100
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
149 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
153 - EUR 400 shared 50% [[mnolan]] EUR 200
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
155 - EUR 250 shared 40% [[mnolan]] EUR 100
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
157 - EUR 300 shared 1/3 [[mnolan]] EUR 100
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
159 - EUR 300 shared 50% [[mnolan]] EUR 150
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
169 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
171 ### Project 2019-02-012 28-apr-2020
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
174 - 6600 scoreboard multi-read/write
176 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
177 - Partitioned equals and greater than comparison
178 - Shared 50% with [[mnolan]]
180 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
181 - partitioned scalar/vector shift
182 - Shared 50% with [[lkcl]]
185 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
188 - auto-parser of POWER9
189 - Shared 50% with [[mnolan]]
192 ### Project 2019-10-029 Date 14mar2020
194 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
196 ### Project 2019-02-012 Date 12mar2020
198 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
199 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
200 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
201 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
203 ### Project 2019-02-012 Date 28jan2020
206 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>