1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
48 - https://bugs.libre-soc.org/show_bug.cgi?id=575
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
57 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
58 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
63 - EUR 50, shared with samuel 10%
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
68 - EUR 50, shared with samuel (EUR 350)
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
81 - MultiCompUnit (and Function Units) proof
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
87 ## Completed but not yet submitted:
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
94 * EUR 1500 (shared with [[tplaten]])
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
96 * EUR 1500 (shared with [[tplaten]])
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
98 * EUR 1000 (shared with [[tplaten]])
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
100 * EUR 500 (shared with [[programmerjake]])
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
102 * EUR 400 (shared with [[programmerjake]])
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
108 - EUR 800 shared with [[klehman]]
109 - EUR 800 shared with [[lkcl]]
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
136 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
140 - (total EUR 400 25% donated by LIP6)
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
144 - shared with [[lxo]]
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
147 - shared with lauri, jacob
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
150 - Shared 50% with Staf
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
153 - Shared with Staf, cole
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
159 - Project 2019-10-043 06dec2020 wishbone
162 ### Project 2019-10-029 14mar2020 coriolis2
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
165 - (total EUR 100 shared 50% with staf)
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
168 - (total EUR 1500 shared 50% with LIP6)
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
171 - (total EUR 400 shared 75% with LIP6)
174 ### Project 2019-02-012 06dec2020 Core
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
177 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
178 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
180 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
183 ### Project 2019-10-043 06dec2020 wishbone
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
186 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
191 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
197 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
201 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
204 - EUR 250 (share with cole)
206 ### Project 2019-10-032 06dec2020 proofs
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
211 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
221 ## Submitted for NLNet RFP
223 submitted 2021-dec-09 but not confirmed paid
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
232 - EUR 800 shared between:
234 - EUR 300 [[tplaten]]
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
236 - EUR 5500 shared between:
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
244 - EUR 500 shared between:
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
251 ### Project 2019-02-012 04sep2020 Core
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
254 - EUR 2000 total, shared with florent. EUR 1200
256 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
260 donation from NLNet confirmed received:
262 ### coriolis2 2021-apr-04
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
266 - shared with Staf 50%
268 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
270 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
271 - EUR 2000, python POWER9 simulator
272 - Shared 50% with [[mnolan]], EUR 1000
273 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
274 - EUR 250, functions needed for simulator
275 - Shared 20% with [[mnolan]], EUR 50
277 ### proofs 2019-10-032
279 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
280 - EUR 500 shared 20% samuel, EUR 100
281 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
282 - EUR 300 shared 1/6 [[mnolan]] EUR 50
283 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
284 - EUR 400 shared 25% [[mnolan]] EUR 100
285 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
288 ### wishbone 2019-10-043
290 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
292 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
294 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
296 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
297 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
298 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
300 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
301 - EUR 400, 50% shared [[programmerjake]] EUR 200
302 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
303 - EUR 750, 33% shared [[programmerjake]] EUR 250
304 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
305 - EUR 200 50% shared, cole, EUR 100
306 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
309 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
310 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
312 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
313 - EUR 400 shared 50% [[mnolan]] EUR 200
314 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
315 - EUR 250 shared 40% [[mnolan]] EUR 100
316 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
317 - EUR 300 shared 1/3 [[mnolan]] EUR 100
318 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
319 - EUR 300 shared 50% [[mnolan]] EUR 150
320 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
322 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
324 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
326 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
328 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
329 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
331 ### Project 2019-02-012 28-apr-2020
333 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
334 - 6600 scoreboard multi-read/write
336 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
337 - Partitioned equals and greater than comparison
338 - Shared 50% with [[mnolan]]
340 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
341 - partitioned scalar/vector shift
342 - Shared 50% with [[lkcl]]
345 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
347 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
348 - auto-parser of POWER9
349 - Shared 50% with [[mnolan]]
352 ### Project 2019-10-029 Date 14mar2020
354 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
357 ### Project 2019-02-012 Date 12mar2020
359 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
360 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
361 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
362 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
364 ### Project 2019-02-012 Date 28jan2020
367 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>