1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
36 - https://bugs.libre-soc.org/show_bug.cgi?id=575
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
45 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
46 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
51 - EUR 50, shared with samuel 10%
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
56 - EUR 50, shared with samuel (EUR 350)
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
69 - MultiCompUnit (and Function Units) proof
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
75 ## Completed but not yet submitted:
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
78 - EUR 800 shared with [[klehman]]
79 - EUR 800 shared with [[lkcl]]
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
81 - EUR 500 shared between:
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
91 - EUR 800 shared between:
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
95 - EUR 5500 shared between:
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
111 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
123 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
126 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
127 - (total EUR 400 25% donated by LIP6)
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
131 - shared with [[lxo]]
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
134 - shared with lauri, jacob
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
137 - Shared 50% with Staf
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
140 - Shared with Staf, cole
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
147 - shared with Staf 50%
148 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
149 - Project 2019-10-043 06dec2020 wishbone
152 ### Project 2019-10-029 14mar2020 coriolis2
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
155 - (total EUR 100 shared 50% with staf)
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
158 - (total EUR 1500 shared 50% with LIP6)
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
161 - (total EUR 400 shared 75% with LIP6)
164 ### Project 2019-02-012 06dec2020 Core
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
167 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
168 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
173 ### Project 2019-10-043 06dec2020 wishbone
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
176 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
183 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
185 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
191 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
194 - EUR 250 (share with cole)
196 ### Project 2019-10-032 06dec2020 proofs
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
211 ## Submitted for NLNet RFP
213 submitted but not confirmed paid:
215 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
217 ### Project 2019-02-012 04sep2020 Core
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
220 - EUR 2000 total, shared with florent. EUR 1200
222 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
226 donation from NLNet confirmed received:
228 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
231 - EUR 2000, python POWER9 simulator
232 - Shared 50% with [[mnolan]], EUR 1000
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
234 - EUR 250, functions needed for simulator
235 - Shared 20% with [[mnolan]], EUR 50
237 ### proofs 2019-10-032
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
240 - EUR 500 shared 20% samuel, EUR 100
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
242 - EUR 300 shared 1/6 [[mnolan]] EUR 50
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
244 - EUR 400 shared 25% [[mnolan]] EUR 100
245 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
248 ### wishbone 2019-10-043
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
256 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
257 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
261 - EUR 400, 50% shared [[programmerjake]] EUR 200
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
263 - EUR 750, 33% shared [[programmerjake]] EUR 250
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
265 - EUR 200 50% shared, cole, EUR 100
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
269 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
270 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
272 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
273 - EUR 400 shared 50% [[mnolan]] EUR 200
274 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
275 - EUR 250 shared 40% [[mnolan]] EUR 100
276 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
277 - EUR 300 shared 1/3 [[mnolan]] EUR 100
278 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
279 - EUR 300 shared 50% [[mnolan]] EUR 150
280 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
284 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
286 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
288 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
289 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
291 ### Project 2019-02-012 28-apr-2020
293 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
294 - 6600 scoreboard multi-read/write
296 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
297 - Partitioned equals and greater than comparison
298 - Shared 50% with [[mnolan]]
300 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
301 - partitioned scalar/vector shift
302 - Shared 50% with [[lkcl]]
305 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
307 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
308 - auto-parser of POWER9
309 - Shared 50% with [[mnolan]]
312 ### Project 2019-10-029 Date 14mar2020
314 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
317 ### Project 2019-02-012 Date 12mar2020
319 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
320 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
321 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
322 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
324 ### Project 2019-02-012 Date 28jan2020
327 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>