1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
9 * <https://libre-soc.org/task_db/>
11 # Priority tasks to keep an eye on
13 * <https://bugs.libre-soc.org/show_bug.cgi?id=864> parallel prefix EUR 3000
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=899> transcendentals sim EUR 4000
15 * <https://bugs.libre-soc.org/show_bug.cgi?id=898> binutils objdump EUR 2500
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=871> Pack/Unpack
18 * <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
20 * <https://bugs.libre-soc.org/show_bug.cgi?id=254> 12500 3D
24 move things along from one stage to the next
26 ## Currently working on
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
56 - EUR 1000 of 1250 shared
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
66 - https://bugs.libre-soc.org/show_bug.cgi?id=575
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
74 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
75 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
80 - EUR 50, shared with samuel 10%
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
85 - EUR 50, shared with samuel (EUR 350)
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
98 - MultiCompUnit (and Function Units) proof
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
104 ## Completed but not yet submitted:
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
111 * EUR 1500 (shared with [[tplaten]])
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
113 * EUR 1500 (shared with [[tplaten]])
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
115 * EUR 1000 (shared with [[tplaten]])
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
117 * EUR 500 (shared with [[programmerjake]])
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
119 * EUR 400 (shared with [[programmerjake]])
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
125 - EUR 800 shared with [[klehman]]
126 - EUR 800 shared with [[lkcl]]
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
130 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
153 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
157 - (total EUR 400 25% donated by LIP6)
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
161 - shared with [[lxo]]
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
164 - shared with lauri, jacob
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
167 - Shared 50% with Staf
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
170 - Shared with Staf, cole
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
176 - Project 2019-10-043 06dec2020 wishbone
179 ### Project 2019-10-029 14mar2020 coriolis2
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
182 - (total EUR 100 shared 50% with staf)
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
185 - (total EUR 1500 shared 50% with LIP6)
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
188 - (total EUR 400 shared 75% with LIP6)
191 ### Project 2019-02-012 06dec2020 Core
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
194 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
195 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
197 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
200 ### Project 2019-10-043 06dec2020 wishbone
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
203 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
204 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
212 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
218 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
221 - EUR 250 (share with cole)
223 ### Project 2019-10-032 06dec2020 proofs
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
238 ## Submitted for NLNet RFP
240 submitted 2021-dec-09 but not confirmed paid
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
247 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
249 - EUR 800 shared between:
251 - EUR 300 [[tplaten]]
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
253 - EUR 5500 shared between:
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
261 - EUR 500 shared between:
265 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
268 ### Project 2019-02-012 04sep2020 Core
270 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
271 - EUR 2000 total, shared with florent. EUR 1200
273 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
277 donation from NLNet confirmed received:
279 ### coriolis2 2021-apr-04
281 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
283 - shared with Staf 50%
285 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
287 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
288 - EUR 2000, python POWER9 simulator
289 - Shared 50% with [[mnolan]], EUR 1000
290 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
291 - EUR 250, functions needed for simulator
292 - Shared 20% with [[mnolan]], EUR 50
294 ### proofs 2019-10-032
296 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
297 - EUR 500 shared 20% samuel, EUR 100
298 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
299 - EUR 300 shared 1/6 [[mnolan]] EUR 50
300 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
301 - EUR 400 shared 25% [[mnolan]] EUR 100
302 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
305 ### wishbone 2019-10-043
307 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
309 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
311 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
313 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
314 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
318 - EUR 400, 50% shared [[programmerjake]] EUR 200
319 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
320 - EUR 750, 33% shared [[programmerjake]] EUR 250
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
322 - EUR 200 50% shared, cole, EUR 100
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
326 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
330 - EUR 400 shared 50% [[mnolan]] EUR 200
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
332 - EUR 250 shared 40% [[mnolan]] EUR 100
333 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
334 - EUR 300 shared 1/3 [[mnolan]] EUR 100
335 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
336 - EUR 300 shared 50% [[mnolan]] EUR 150
337 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
339 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
341 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
343 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
345 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
346 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
348 ### Project 2019-02-012 28-apr-2020
350 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
351 - 6600 scoreboard multi-read/write
353 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
354 - Partitioned equals and greater than comparison
355 - Shared 50% with [[mnolan]]
357 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
358 - partitioned scalar/vector shift
359 - Shared 50% with [[lkcl]]
362 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
364 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
365 - auto-parser of POWER9
366 - Shared 50% with [[mnolan]]
369 ### Project 2019-10-029 Date 14mar2020
371 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
374 ### Project 2019-02-012 Date 12mar2020
376 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
377 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
378 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
379 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
381 ### Project 2019-02-012 Date 28jan2020
384 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>