1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
25 - https://bugs.libre-soc.org/show_bug.cgi?id=575
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
34 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
35 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
40 - EUR 50, shared with samuel 10%
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
45 - EUR 50, shared with samuel (EUR 350)
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
58 - MultiCompUnit (and Function Units) proof
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
64 ## Completed but not yet submitted:
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
71 - EUR 800 shared between:
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
75 - EUR 5000 shared between:
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
103 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
107 - (total EUR 400 25% donated by LIP6)
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
111 - shared with [[lxo]]
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
114 - shared with lauri, jacob
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
117 - Shared 50% with Staf
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
120 - Shared with Staf, cole
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
125 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
127 - shared with Staf 50%
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
129 - Project 2019-10-043 06dec2020 wishbone
132 ### Project 2019-10-029 14mar2020 coriolis2
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
135 - (total EUR 100 shared 50% with staf)
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
138 - (total EUR 1500 shared 50% with LIP6)
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
141 - (total EUR 400 shared 75% with LIP6)
144 ### Project 2019-02-012 06dec2020 Core
146 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
147 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
148 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
153 ### Project 2019-10-043 06dec2020 wishbone
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
156 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
161 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
167 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
169 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
171 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
174 - EUR 250 (share with cole)
176 ### Project 2019-10-032 06dec2020 proofs
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
191 ## Submitted for NLNet RFP
193 submitted but not confirmed paid:
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
197 ### Project 2019-02-012 04sep2020 Core
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
200 - EUR 2000 total, shared with florent. EUR 1200
202 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
206 donation from NLNet confirmed received:
208 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
211 - EUR 2000, python POWER9 simulator
212 - Shared 50% with [[mnolan]], EUR 1000
213 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
214 - EUR 250, functions needed for simulator
215 - Shared 20% with [[mnolan]], EUR 50
217 ### proofs 2019-10-032
219 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
220 - EUR 500 shared 20% samuel, EUR 100
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
222 - EUR 300 shared 1/6 [[mnolan]] EUR 50
223 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
224 - EUR 400 shared 25% [[mnolan]] EUR 100
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
228 ### wishbone 2019-10-043
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
236 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
237 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
241 - EUR 400, 50% shared [[programmerjake]] EUR 200
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
243 - EUR 750, 33% shared [[programmerjake]] EUR 250
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
245 - EUR 200 50% shared, cole, EUR 100
246 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
249 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
253 - EUR 400 shared 50% [[mnolan]] EUR 200
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
255 - EUR 250 shared 40% [[mnolan]] EUR 100
256 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
257 - EUR 300 shared 1/3 [[mnolan]] EUR 100
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
259 - EUR 300 shared 50% [[mnolan]] EUR 150
260 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
269 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
271 ### Project 2019-02-012 28-apr-2020
273 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
274 - 6600 scoreboard multi-read/write
276 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
277 - Partitioned equals and greater than comparison
278 - Shared 50% with [[mnolan]]
280 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
281 - partitioned scalar/vector shift
282 - Shared 50% with [[lkcl]]
285 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
287 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
288 - auto-parser of POWER9
289 - Shared 50% with [[mnolan]]
292 ### Project 2019-10-029 Date 14mar2020
294 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
297 ### Project 2019-02-012 Date 12mar2020
299 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
300 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
301 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
302 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
304 ### Project 2019-02-012 Date 28jan2020
307 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>