1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
10 move things along from one stage to the next
12 ## Currently working on
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
18 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
19 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
24 - EUR 50, shared with samuel 10%
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
29 - EUR 50, shared with samuel (EUR 350)
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
35 - EUR 400 shared 25% [[mnolan]] EUR 100
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
37 - EUR 500 shared [[mnolan]] samuel, TBD split
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST cache-inhibit
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
42 - EUR 250 (share with cole)
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
47 ## Completed but not yet submitted:
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
50 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST sign-extend
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
68 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
70 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
72 - functions needed for simulator
73 - Shared 90% with [[lkcl]]
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> parent #198
75 - Formal proof of decoder
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> parent #195
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> parent #195
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> parent #195
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> parent #195
84 - POWER9 LOGICAL proof
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> parent #195
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
88 - MultiCompUnit (and Function Units) proof
90 ## Submitted for NLNet RFP
92 submitted but not confirmed paid:
94 ### Project 2019-02-012 04sep2020 Core
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
97 - EUR 2000 total, shared with florent. EUR 1200
99 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
103 donation from NLNet confirmed received:
105 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
108 - EUR 2000, python POWER9 simulator
109 - Shared 50% with [[mnolan]], EUR 1000
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
111 - EUR 250, functions needed for simulator
112 - Shared 20% with [[mnolan]], EUR 50
114 #### proofs 2019-10-032
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
117 - EUR 500 shared 20% samuel, EUR 100
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
119 - EUR 300 shared 1/6 [[mnolan]] EUR 50
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
121 - EUR 400 shared 25% [[mnolan]] EUR 100
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
125 ### wishbone 2019-10-043
127 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
131 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
133 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
134 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
138 - EUR 400, 50% shared [[programmerjake]] EUR 200
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
140 - EUR 750, 33% shared [[programmerjake]] EUR 250
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
142 - EUR 200 50% shared, cole, EUR 100
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
146 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
149 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
150 - EUR 400 shared 50% [[mnolan]] EUR 200
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
152 - EUR 250 shared 40% [[mnolan]] EUR 100
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
154 - EUR 300 shared 1/3 [[mnolan]] EUR 100
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
156 - EUR 300 shared 50% [[mnolan]] EUR 150
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
161 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
163 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
166 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
168 ### Project 2019-02-012 28-apr-2020
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
171 - 6600 scoreboard multi-read/write
173 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
174 - Partitioned equals and greater than comparison
175 - Shared 50% with [[mnolan]]
177 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
178 - partitioned scalar/vector shift
179 - Shared 50% with [[lkcl]]
182 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
185 - auto-parser of POWER9
186 - Shared 50% with [[mnolan]]
189 ### Project 2019-10-029 Date 14mar2020
191 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
193 ### Project 2019-02-012 Date 12mar2020
195 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
196 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
197 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
198 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
200 ### Project 2019-02-012 Date 28jan2020
203 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>