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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
19 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
20 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
23 - shared with cole
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
33 - EUR 300
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
40 - EUR 400 shared 25% [[mnolan]] EUR 100
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
42 - EUR 500 shared [[mnolan]] samuel, TBD split
43
44 ## Completed but not yet submitted:
45
46 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
47
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
49 - EUR 2000, python POWER9 simulator
50 - Shared 50% with [[mnolan]], EUR 1000
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
52 - EUR 250, functions needed for simulator
53 - Shared 20% with [[mnolan]], EUR 50
54
55 #### proofs 2019-10-032
56
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
58 - EUR 500 shared 20% samuel, EUR 100
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
60 - EUR 300 shared 1/6 [[mnolan]] EUR 50
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
62 - EUR 400 shared 25% [[mnolan]] EUR 100
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
64 - EUR 150
65
66 ### wishbone 2019-10-043
67
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
69 - EUR 500
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
71 - EUR 300
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
73 - EUR 250
74 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
75 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
77 - EUR 300
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
79 - EUR 400, 50% shared [[programmerjake]] EUR 200
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
81 - EUR 750, 33% shared [[programmerjake]] EUR 250
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
83 - EUR 200 50% shared, cole, EUR 100
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
85 - EUR 200
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
87 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
89 - EUR 150
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
91 - EUR 400 shared 50% [[mnolan]] EUR 200
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
93 - EUR 250 shared 40% [[mnolan]] EUR 100
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
95 - EUR 300 shared 1/3 [[mnolan]] EUR 100
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
97 - EUR 300 shared 50% [[mnolan]] EUR 150
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
99 - EUR 750
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
101 - EUR 100
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
103 - EUR 100
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
105 - EUR 100
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
107 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
108
109 ## Submitted for NLNet RFP
110
111 submitted but not confirmed paid:
112
113 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
114
115 ## Paid
116
117 donation from NLNet confirmed received:
118
119 ### Project 2019-02-012 28-apr-2020
120
121 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
122 - 6600 scoreboard multi-read/write
123 - EUR 600
124 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
125 - Partitioned equals and greater than comparison
126 - Shared 50% with [[mnolan]]
127 - EUR 200 (each)
128 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
129 - partitioned scalar/vector shift
130 - Shared 50% with [[lkcl]]
131 - EUR 350 (each)
132
133 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
134
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
136 - auto-parser of POWER9
137 - Shared 50% with [[mnolan]]
138 - EUR 500 (each)
139
140 ### Project 2019-10-029 Date 14mar2020
141
142 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
143
144 ### Project 2019-02-012 Date 12mar2020
145
146 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
147 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
148 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
149 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
150
151 ### Project 2019-02-012 Date 28jan2020
152
153 * admin tasks
154 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
155