1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
12 move things along from one stage to the next
14 ## Currently working on
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
25 - https://bugs.libre-soc.org/show_bug.cgi?id=575
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
34 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
35 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
40 - EUR 50, shared with samuel 10%
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
45 - EUR 50, shared with samuel (EUR 350)
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
58 - MultiCompUnit (and Function Units) proof
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
64 ## Completed but not yet submitted:
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
69 - EUR 800 shared between:
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
98 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
102 - (total EUR 400 25% donated by LIP6)
104 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
106 - shared with [[lxo]]
107 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
109 - shared with lauri, jacob
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
112 - Shared 50% with Staf
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
115 - Shared with Staf, cole
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
122 - shared with Staf 50%
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
124 - Project 2019-10-043 06dec2020 wishbone
127 ### Project 2019-10-029 14mar2020 coriolis2
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
130 - (total EUR 100 shared 50% with staf)
132 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
133 - (total EUR 1500 shared 50% with LIP6)
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
136 - (total EUR 400 shared 75% with LIP6)
139 ### Project 2019-02-012 06dec2020 Core
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
142 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
143 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
148 ### Project 2019-10-043 06dec2020 wishbone
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
151 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
152 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
154 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
158 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
166 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
169 - EUR 250 (share with cole)
171 ### Project 2019-10-032 06dec2020 proofs
173 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
179 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
186 ## Submitted for NLNet RFP
188 submitted but not confirmed paid:
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
192 ### Project 2019-02-012 04sep2020 Core
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
195 - EUR 2000 total, shared with florent. EUR 1200
197 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
201 donation from NLNet confirmed received:
203 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
205 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
206 - EUR 2000, python POWER9 simulator
207 - Shared 50% with [[mnolan]], EUR 1000
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
209 - EUR 250, functions needed for simulator
210 - Shared 20% with [[mnolan]], EUR 50
212 ### proofs 2019-10-032
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
215 - EUR 500 shared 20% samuel, EUR 100
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
217 - EUR 300 shared 1/6 [[mnolan]] EUR 50
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
219 - EUR 400 shared 25% [[mnolan]] EUR 100
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
223 ### wishbone 2019-10-043
225 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
227 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
229 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
231 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
232 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
233 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
235 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
236 - EUR 400, 50% shared [[programmerjake]] EUR 200
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
238 - EUR 750, 33% shared [[programmerjake]] EUR 250
239 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
240 - EUR 200 50% shared, cole, EUR 100
241 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
243 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
244 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
245 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
247 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
248 - EUR 400 shared 50% [[mnolan]] EUR 200
249 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
250 - EUR 250 shared 40% [[mnolan]] EUR 100
251 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
252 - EUR 300 shared 1/3 [[mnolan]] EUR 100
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
254 - EUR 300 shared 50% [[mnolan]] EUR 150
255 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
257 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
259 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
261 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
264 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
266 ### Project 2019-02-012 28-apr-2020
268 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
269 - 6600 scoreboard multi-read/write
271 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
272 - Partitioned equals and greater than comparison
273 - Shared 50% with [[mnolan]]
275 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
276 - partitioned scalar/vector shift
277 - Shared 50% with [[lkcl]]
280 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
282 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
283 - auto-parser of POWER9
284 - Shared 50% with [[mnolan]]
287 ### Project 2019-10-029 Date 14mar2020
289 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
292 ### Project 2019-02-012 Date 12mar2020
294 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
295 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
296 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
297 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
299 ### Project 2019-02-012 Date 28jan2020
302 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>