1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
8 * <http://twitter.com/lkcl>
10 # Priority tasks to keep an eye on
12 * <https://bugs.libre-soc.org/show_bug.cgi?id=236> Atomics, Jacob
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=195> Power ISA Formal Proof
16 * <https://bugs.libre-soc.org/show_bug.cgi?id=728> ISACaller, Dmitry
18 * <https://bugs.libre-soc.org/show_bug.cgi?id=758> Pack/Unpack
20 * <https://bugs.libre-soc.org/show_bug.cgi?id=758> pypowersim, Andrey
22 * <https://bugs.libre-soc.org/show_bug.cgi?id=198> nmutil/etc Formal Proofs
24 * <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
30 move things along from one stage to the next
32 ## Currently working on
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
62 - EUR 1000 of 1250 shared
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
72 - https://bugs.libre-soc.org/show_bug.cgi?id=575
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
80 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
81 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
83 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
85 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
86 - EUR 50, shared with samuel 10%
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
91 - EUR 50, shared with samuel (EUR 350)
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
104 - MultiCompUnit (and Function Units) proof
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
108 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
110 ## Completed but not yet submitted:
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
117 * EUR 1500 (shared with [[tplaten]])
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
119 * EUR 1500 (shared with [[tplaten]])
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
121 * EUR 1000 (shared with [[tplaten]])
122 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
123 * EUR 500 (shared with [[programmerjake]])
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
125 * EUR 400 (shared with [[programmerjake]])
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
131 - EUR 800 shared with [[klehman]]
132 - EUR 800 shared with [[lkcl]]
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
136 - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
138 - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
142 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
150 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
159 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
163 - (total EUR 400 25% donated by LIP6)
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
167 - shared with [[lxo]]
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
170 - shared with lauri, jacob
171 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
173 - Shared 50% with Staf
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
176 - Shared with Staf, cole
177 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
180 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
181 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
182 - Project 2019-10-043 06dec2020 wishbone
185 ### Project 2019-10-029 14mar2020 coriolis2
187 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
188 - (total EUR 100 shared 50% with staf)
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
191 - (total EUR 1500 shared 50% with LIP6)
193 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
194 - (total EUR 400 shared 75% with LIP6)
197 ### Project 2019-02-012 06dec2020 Core
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
200 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
201 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
206 ### Project 2019-10-043 06dec2020 wishbone
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
209 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
212 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
224 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
227 - EUR 250 (share with cole)
229 ### Project 2019-10-032 06dec2020 proofs
231 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
237 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
244 ## Submitted for NLNet RFP
246 submitted 2021-dec-09 but not confirmed paid
248 - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
250 - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
252 - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
253 - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
254 - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
255 - EUR 800 shared between:
257 - EUR 300 [[tplaten]]
258 - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
259 - EUR 5500 shared between:
262 - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
264 - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
266 - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
267 - EUR 500 shared between:
271 - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
274 ### Project 2019-02-012 04sep2020 Core
276 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
277 - EUR 2000 total, shared with florent. EUR 1200
279 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
283 donation from NLNet confirmed received:
285 ### coriolis2 2021-apr-04
287 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
289 - shared with Staf 50%
291 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
293 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
294 - EUR 2000, python POWER9 simulator
295 - Shared 50% with [[mnolan]], EUR 1000
296 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
297 - EUR 250, functions needed for simulator
298 - Shared 20% with [[mnolan]], EUR 50
300 ### proofs 2019-10-032
302 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
303 - EUR 500 shared 20% samuel, EUR 100
304 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
305 - EUR 300 shared 1/6 [[mnolan]] EUR 50
306 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
307 - EUR 400 shared 25% [[mnolan]] EUR 100
308 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
311 ### wishbone 2019-10-043
313 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
315 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
317 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
319 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
320 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
321 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
323 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
324 - EUR 400, 50% shared [[programmerjake]] EUR 200
325 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
326 - EUR 750, 33% shared [[programmerjake]] EUR 250
327 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
328 - EUR 200 50% shared, cole, EUR 100
329 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
331 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
332 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
333 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
335 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
336 - EUR 400 shared 50% [[mnolan]] EUR 200
337 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
338 - EUR 250 shared 40% [[mnolan]] EUR 100
339 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
340 - EUR 300 shared 1/3 [[mnolan]] EUR 100
341 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
342 - EUR 300 shared 50% [[mnolan]] EUR 150
343 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
345 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
347 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
349 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
351 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
352 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
354 ### Project 2019-02-012 28-apr-2020
356 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
357 - 6600 scoreboard multi-read/write
359 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
360 - Partitioned equals and greater than comparison
361 - Shared 50% with [[mnolan]]
363 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
364 - partitioned scalar/vector shift
365 - Shared 50% with [[lkcl]]
368 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
370 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
371 - auto-parser of POWER9
372 - Shared 50% with [[mnolan]]
375 ### Project 2019-10-029 Date 14mar2020
377 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
380 ### Project 2019-02-012 Date 12mar2020
382 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
383 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
384 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
385 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
387 ### Project 2019-02-012 Date 28jan2020
390 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>