lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7
   8 # Status tracking
   9
  10 move things along from one stage to the next
  11
  12 ## Currently working on
  13
  14  - Project Management
  15  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  16  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  17  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder with [[mnolan]]
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
  19     - functions needed for simulator
  20     - Shared 10% with [[mnolan]]
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> test core to regfiles
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
  40    - EUR 400 shared 25% [[mnolan]] EUR 100
  41
  42 ## Completed but not yet submitted:
  43
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
  48    - EUR 400 shared 50% [[mnolan]] EUR 200
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
  50    - EUR 500 shared [[mnolan]] samuel, TBD split
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
  52    - EUR 250 shared 40% [[mnolan]] EUR 100
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
  60  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
  62  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
  63     - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
  64  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
  65
  66 ## Submitted for NLNet RFP
  67
  68 submitted but not confirmed paid:
  69
  70 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
  71
  72 ## Paid
  73
  74 donation from NLNet confirmed received:
  75
  76 ### Project 2019-02-012 28-apr-2020
  77
  78  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
  79    - 6600 scoreboard multi-read/write
  80    - EUR 600
  81  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
  82    - Partitioned equals and greater than comparison
  83    - Shared 50% with [[mnolan]]
  84    - EUR 200 (each)
  85  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
  86    - partitioned scalar/vector shift
  87    - Shared 50% with [[lkcl]]
  88    - EUR 350 (each)
  89
  90 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
  91
  92  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
  93     - auto-parser of POWER9
  94     - Shared 50% with [[mnolan]]
  95     - EUR 500 (each)
  96
  97 ### Project 2019-10-029 Date 14mar2020
  98
  99 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
 100
 101 ### Project 2019-02-012 Date 12mar2020
 102
 103 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 104 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 105 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 106 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 107
 108 ### Project 2019-02-012 Date 28jan2020
 109
 110 * admin tasks
 111 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 112