1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
11 move things along from one stage to the next
13 ## Currently working on
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
19 - https://bugs.libre-soc.org/show_bug.cgi?id=575
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
32 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
33 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
38 - EUR 50, shared with samuel 10%
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
43 - EUR 50, shared with samuel (EUR 350)
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
61 - MultiCompUnit (and Function Units) proof
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
67 ## Completed but not yet submitted:
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
81 - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
85 - (total EUR 400 25% donated by LIP6)
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
92 - shared with lauri, jacob
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
95 - Shared 50% with Staf
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
98 - Shared with Staf, cole
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
102 - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
105 - shared with Staf 50%
106 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
107 - Project 2019-10-043 06dec2020 wishbone
110 ### Project 2019-10-029 14mar2020 coriolis2
112 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
113 - (total EUR 100 shared 50% with staf)
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
116 - (total EUR 1500 shared 50% with LIP6)
118 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
119 - (total EUR 400 shared 75% with LIP6)
122 ### Project 2019-02-012 06dec2020 Core
124 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
125 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
126 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
128 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
131 ### Project 2019-10-043 06dec2020 wishbone
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
134 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
135 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
137 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
139 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
141 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
145 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
149 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
152 - EUR 250 (share with cole)
154 ### Project 2019-10-032 06dec2020 proofs
156 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
165 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
169 ## Submitted for NLNet RFP
171 submitted but not confirmed paid:
173 ### Project 2019-02-012 04sep2020 Core
175 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
176 - EUR 2000 total, shared with florent. EUR 1200
178 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
182 donation from NLNet confirmed received:
184 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
187 - EUR 2000, python POWER9 simulator
188 - Shared 50% with [[mnolan]], EUR 1000
189 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
190 - EUR 250, functions needed for simulator
191 - Shared 20% with [[mnolan]], EUR 50
193 ### proofs 2019-10-032
195 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
196 - EUR 500 shared 20% samuel, EUR 100
197 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
198 - EUR 300 shared 1/6 [[mnolan]] EUR 50
199 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
200 - EUR 400 shared 25% [[mnolan]] EUR 100
201 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
204 ### wishbone 2019-10-043
206 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
208 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
210 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
212 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
213 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
214 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
216 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
217 - EUR 400, 50% shared [[programmerjake]] EUR 200
218 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
219 - EUR 750, 33% shared [[programmerjake]] EUR 250
220 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
221 - EUR 200 50% shared, cole, EUR 100
222 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
224 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
225 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
226 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
228 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
229 - EUR 400 shared 50% [[mnolan]] EUR 200
230 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
231 - EUR 250 shared 40% [[mnolan]] EUR 100
232 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
233 - EUR 300 shared 1/3 [[mnolan]] EUR 100
234 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
235 - EUR 300 shared 50% [[mnolan]] EUR 150
236 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
238 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
240 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
242 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
244 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
245 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
247 ### Project 2019-02-012 28-apr-2020
249 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
250 - 6600 scoreboard multi-read/write
252 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
253 - Partitioned equals and greater than comparison
254 - Shared 50% with [[mnolan]]
256 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
257 - partitioned scalar/vector shift
258 - Shared 50% with [[lkcl]]
261 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
263 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
264 - auto-parser of POWER9
265 - Shared 50% with [[mnolan]]
268 ### Project 2019-10-029 Date 14mar2020
270 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
273 ### Project 2019-02-012 Date 12mar2020
275 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
276 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
277 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
278 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
280 ### Project 2019-02-012 Date 28jan2020
283 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>