1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
10 move things along from one stage to the next
12 ## Currently working on
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcodes
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
28 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
29 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
34 - EUR 50, shared with samuel 10%
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
39 - EUR 50, shared with samuel (EUR 350)
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
57 - MultiCompUnit (and Function Units) proof
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
62 ## Completed but not yet submitted:
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
65 - Project 2019-10-043 06dec2020 wishbone
68 ### Project 2019-10-029 14mar2020 coriolis2
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
71 - (total EUR 100 shared 50% with staf)
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
74 - (total EUR 1500 shared 50% with LIP6)
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
77 - (total EUR 400 shared 75% with LIP6)
80 ### Project 2019-02-012 06dec2020 Core
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
83 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
84 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
89 ### Project 2019-10-043 06dec2020 wishbone
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
92 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
103 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
107 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
109 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
110 - EUR 250 (share with cole)
112 ### Project 2019-10-032 06dec2020 proofs
114 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
117 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
123 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
127 ## Submitted for NLNet RFP
129 submitted but not confirmed paid:
131 ### Project 2019-02-012 04sep2020 Core
133 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
134 - EUR 2000 total, shared with florent. EUR 1200
136 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
140 donation from NLNet confirmed received:
142 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
144 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
145 - EUR 2000, python POWER9 simulator
146 - Shared 50% with [[mnolan]], EUR 1000
147 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
148 - EUR 250, functions needed for simulator
149 - Shared 20% with [[mnolan]], EUR 50
151 ### proofs 2019-10-032
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
154 - EUR 500 shared 20% samuel, EUR 100
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
156 - EUR 300 shared 1/6 [[mnolan]] EUR 50
157 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
158 - EUR 400 shared 25% [[mnolan]] EUR 100
159 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
162 ### wishbone 2019-10-043
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
166 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
170 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
171 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
175 - EUR 400, 50% shared [[programmerjake]] EUR 200
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
177 - EUR 750, 33% shared [[programmerjake]] EUR 250
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
179 - EUR 200 50% shared, cole, EUR 100
180 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
183 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
187 - EUR 400 shared 50% [[mnolan]] EUR 200
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
189 - EUR 250 shared 40% [[mnolan]] EUR 100
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
191 - EUR 300 shared 1/3 [[mnolan]] EUR 100
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
193 - EUR 300 shared 50% [[mnolan]] EUR 150
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
200 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
202 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
203 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
205 ### Project 2019-02-012 28-apr-2020
207 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
208 - 6600 scoreboard multi-read/write
210 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
211 - Partitioned equals and greater than comparison
212 - Shared 50% with [[mnolan]]
214 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
215 - partitioned scalar/vector shift
216 - Shared 50% with [[lkcl]]
219 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
221 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
222 - auto-parser of POWER9
223 - Shared 50% with [[mnolan]]
226 ### Project 2019-10-029 Date 14mar2020
228 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
231 ### Project 2019-02-012 Date 12mar2020
233 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
234 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
235 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
236 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
238 ### Project 2019-02-012 Date 28jan2020
241 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>