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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
16 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
17 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder with [[mnolan]]
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
19 - functions needed for simulator
20 - Shared 10% with [[mnolan]]
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
23 - shared with cole
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
40 - EUR 400 shared 25% [[mnolan]] EUR 100
41
42 ## Completed but not yet submitted:
43
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
45 - EUR 300
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
47 - EUR 400, 50% shared [[programmerjake]] EUR 200
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
49 - EUR 750, 33% shared [[programmerjake]] EUR 250
50 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
51 - EUR 200 50% shared, cole, EUR 100
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
53 - EUR 200
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
55 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
56 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
57 - EUR 500 shared 20% samuel, EUR 100
58 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
59 - EUR 150
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
61 - EUR 400 shared 50% [[mnolan]] EUR 200
62 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
63 - EUR 500 shared [[mnolan]] samuel, TBD split
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
65 - EUR 250 shared 40% [[mnolan]] EUR 100
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
67 - EUR 300 shared 1/3 [[mnolan]] EUR 100
68 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
69 - EUR 300 shared 1/6 [[mnolan]] EUR 50
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
71 - EUR 300 shared 50% [[mnolan]] EUR 150
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
73 - EUR 400 shared 25% [[mnolan]] EUR 100
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
75 - EUR 150
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
77 - EUR 750
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
79 - EUR 100
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
81 - EUR 100
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
83 - EUR 100
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
85 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
87 - EUR 500
88
89 ## Submitted for NLNet RFP
90
91 submitted but not confirmed paid:
92
93 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
94
95 ## Paid
96
97 donation from NLNet confirmed received:
98
99 ### Project 2019-02-012 28-apr-2020
100
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
102 - 6600 scoreboard multi-read/write
103 - EUR 600
104 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
105 - Partitioned equals and greater than comparison
106 - Shared 50% with [[mnolan]]
107 - EUR 200 (each)
108 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
109 - partitioned scalar/vector shift
110 - Shared 50% with [[lkcl]]
111 - EUR 350 (each)
112
113 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
114
115 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
116 - auto-parser of POWER9
117 - Shared 50% with [[mnolan]]
118 - EUR 500 (each)
119
120 ### Project 2019-10-029 Date 14mar2020
121
122 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
123
124 ### Project 2019-02-012 Date 12mar2020
125
126 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
127 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
128 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
129 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
130
131 ### Project 2019-02-012 Date 28jan2020
132
133 * admin tasks
134 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
135