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[libreriscv.git] / lkcl.mdwn
1 # Luke Kenneth Casson Leighton
2
3 Lead dev and Project Coordinator for Libre-SOC.
4
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
7
8 # Status tracking
9
10 move things along from one stage to the next
11
12 ## Currently working on
13
14 - Project Management
15 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
16 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
17 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder with [[mnolan]]
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
19 - functions needed for simulator
20 - Shared 10% with [[mnolan]]
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> test core to regfiles
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
25 - shared with cole
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
41 - EUR 400 shared 25% [[mnolan]] EUR 100
42
43 ## Completed but not yet submitted:
44
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
46 - EUR 200 50% shared, cole, EUR 100
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
48 - EUR 200
49 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
50 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
52 - EUR 500 shared 20% samuel, EUR 100
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
54 - EUR 150
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
56 - EUR 400 shared 50% [[mnolan]] EUR 200
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
58 - EUR 500 shared [[mnolan]] samuel, TBD split
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
60 - EUR 250 shared 40% [[mnolan]] EUR 100
61 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
62 - EUR 300 shared 1/3 [[mnolan]] EUR 100
63 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
64 - EUR 300 shared 1/6 [[mnolan]] EUR 50
65 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
66 - EUR 300 shared 50% [[mnolan]] EUR 150
67 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
68 - EUR 400 shared 25% [[mnolan]] EUR 100
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
70 - EUR 150
71 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
72 - EUR 750
73 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
74 - EUR 100
75 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
76 - EUR 100
77 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
78 - EUR 100
79 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
80 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
81 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
82 - EUR 500
83
84 ## Submitted for NLNet RFP
85
86 submitted but not confirmed paid:
87
88 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
89
90 ## Paid
91
92 donation from NLNet confirmed received:
93
94 ### Project 2019-02-012 28-apr-2020
95
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
97 - 6600 scoreboard multi-read/write
98 - EUR 600
99 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
100 - Partitioned equals and greater than comparison
101 - Shared 50% with [[mnolan]]
102 - EUR 200 (each)
103 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
104 - partitioned scalar/vector shift
105 - Shared 50% with [[lkcl]]
106 - EUR 350 (each)
107
108 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
109
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
111 - auto-parser of POWER9
112 - Shared 50% with [[mnolan]]
113 - EUR 500 (each)
114
115 ### Project 2019-10-029 Date 14mar2020
116
117 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
118
119 ### Project 2019-02-012 Date 12mar2020
120
121 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
122 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
123 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
124 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
125
126 ### Project 2019-02-012 Date 28jan2020
127
128 * admin tasks
129 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
130