lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7
   8 # Status tracking
   9
  10 move things along from one stage to the next
  11
  12 ## Currently working on
  13
  14  - Project Management
  15  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  16  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  17  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder with [[mnolan]]
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
  19     - functions needed for simulator
  20     - Shared 10% with [[mnolan]]
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> test core to regfiles
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  26  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  30  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
  37  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
  38  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  39
  40 ## Completed but not yet submitted:
  41
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
  43  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
  46    - EUR 400 shared 50% [[mnolan]] EUR 200
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
  48  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
  55  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
  58  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
  59  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
  60     - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
  62
  63 ## Submitted for NLNet RFP
  64
  65 submitted but not confirmed paid:
  66
  67 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
  68
  69 ## Paid
  70
  71 donation from NLNet confirmed received:
  72
  73 ### Project 2019-02-012 28-apr-2020
  74
  75  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
  76    - 6600 scoreboard multi-read/write
  77    - EUR 600
  78  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
  79    - Partitioned equals and greater than comparison
  80    - Shared 50% with [[mnolan]]
  81    - EUR 200 (each)
  82  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
  83    - partitioned scalar/vector shift
  84    - Shared 50% with [[lkcl]]
  85    - EUR 350 (each)
  86
  87 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
  88
  89  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
  90     - auto-parser of POWER9
  91     - Shared 50% with [[mnolan]]
  92     - EUR 500 (each)
  93
  94 ### Project 2019-10-029 Date 14mar2020
  95
  96 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
  97
  98 ### Project 2019-02-012 Date 12mar2020
  99
 100 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 101 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 102 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 103 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 104
 105 ### Project 2019-02-012 Date 28jan2020
 106
 107 * admin tasks
 108 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 109