1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
10 move things along from one stage to the next
12 ## Currently working on
15 - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
16 - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
17 - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
20 - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
24 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
25 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
30 - EUR 50, shared with samuel 10%
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
35 - EUR 50, shared with samuel (EUR 350)
36 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
37 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
38 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
39 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
40 - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
41 - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
43 - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
44 - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
46 - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
47 - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
48 - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
52 - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
53 - MultiCompUnit (and Function Units) proof
54 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
58 ## Completed but not yet submitted:
60 - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
61 - Project 2019-10-043 06dec2020 wishbone
64 ### Project 2019-10-029 14mar2020 coriolis2
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
67 - (total EUR 100 shared 50% with staf)
69 - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
70 - (total EUR 1500 shared 50% with LIP6)
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
73 - (total EUR 400 shared 75% with LIP6)
76 ### Project 2019-02-012 06dec2020 Core
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
79 - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
80 - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
85 ### Project 2019-10-043 06dec2020 wishbone
87 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
88 - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
89 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
91 - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
93 - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
95 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
97 - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
99 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
101 - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
103 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
106 - EUR 250 (share with cole)
108 ### Project 2019-10-032 06dec2020 proofs
110 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
113 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
116 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
119 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
123 ## Submitted for NLNet RFP
125 submitted but not confirmed paid:
127 ### Project 2019-02-012 04sep2020 Core
129 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
130 - EUR 2000 total, shared with florent. EUR 1200
132 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
136 donation from NLNet confirmed received:
138 ### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
140 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
141 - EUR 2000, python POWER9 simulator
142 - Shared 50% with [[mnolan]], EUR 1000
143 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
144 - EUR 250, functions needed for simulator
145 - Shared 20% with [[mnolan]], EUR 50
147 ### proofs 2019-10-032
149 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
150 - EUR 500 shared 20% samuel, EUR 100
151 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
152 - EUR 300 shared 1/6 [[mnolan]] EUR 50
153 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
154 - EUR 400 shared 25% [[mnolan]] EUR 100
155 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
158 ### wishbone 2019-10-043
160 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
162 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
164 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
166 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
167 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
168 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
170 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
171 - EUR 400, 50% shared [[programmerjake]] EUR 200
172 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
173 - EUR 750, 33% shared [[programmerjake]] EUR 250
174 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
175 - EUR 200 50% shared, cole, EUR 100
176 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
178 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
179 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
180 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
182 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
183 - EUR 400 shared 50% [[mnolan]] EUR 200
184 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
185 - EUR 250 shared 40% [[mnolan]] EUR 100
186 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
187 - EUR 300 shared 1/3 [[mnolan]] EUR 100
188 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
189 - EUR 300 shared 50% [[mnolan]] EUR 150
190 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
192 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
194 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
196 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
198 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
199 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
201 ### Project 2019-02-012 28-apr-2020
203 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
204 - 6600 scoreboard multi-read/write
206 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
207 - Partitioned equals and greater than comparison
208 - Shared 50% with [[mnolan]]
210 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
211 - partitioned scalar/vector shift
212 - Shared 50% with [[lkcl]]
215 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
217 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
218 - auto-parser of POWER9
219 - Shared 50% with [[mnolan]]
222 ### Project 2019-10-029 Date 14mar2020
224 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
227 ### Project 2019-02-012 Date 12mar2020
229 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
230 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
231 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
232 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
234 ### Project 2019-02-012 Date 28jan2020
237 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>