1 # Luke Kenneth Casson Leighton
3 Lead dev and Project Coordinator for Libre-SOC.
5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
10 move things along from one stage to the next
12 ## Currently working on
15 - https://bugs.libre-soc.org/show_bug.cgi?id=425
16 - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
17 - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
18 - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
19 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
21 - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
22 - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
23 - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
24 - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
25 - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
26 - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
27 - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
28 - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
29 - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
30 - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
31 - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
32 - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
33 - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
34 - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
35 - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
36 - EUR 400 shared 25% [[mnolan]] EUR 100
38 ## Completed but not yet submitted:
40 ### 2019-10P-046 19-aug-2020 NLNet 2019 Formal Standards OpenPOWER
42 - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
43 - EUR 2000, python POWER9 simulator
44 - Shared 50% with [[mnolan]], EUR 1000
45 - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
46 - EUR 250, functions needed for simulator
47 - Shared 20% with [[mnolan]], EUR 50
51 - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
52 - EUR 500 shared 20% samuel, EUR 100
53 - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
54 - EUR 500 shared [[mnolan]] samuel, TBD split
55 - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
56 - EUR 300 shared 1/6 [[mnolan]] EUR 50
57 - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
58 - EUR 400 shared 25% [[mnolan]] EUR 100
59 - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
64 - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
66 - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
68 - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
69 - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
70 - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
72 - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
73 - EUR 400, 50% shared [[programmerjake]] EUR 200
74 - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
75 - EUR 750, 33% shared [[programmerjake]] EUR 250
76 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
77 - EUR 200 50% shared, cole, EUR 100
78 - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
80 - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
81 - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
82 - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
84 - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
85 - EUR 400 shared 50% [[mnolan]] EUR 200
86 - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
87 - EUR 250 shared 40% [[mnolan]] EUR 100
88 - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
89 - EUR 300 shared 1/3 [[mnolan]] EUR 100
90 - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
91 - EUR 300 shared 50% [[mnolan]] EUR 150
92 - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
94 - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
96 - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
98 - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
100 - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
101 - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
105 - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
108 ## Submitted for NLNet RFP
110 submitted but not confirmed paid:
112 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
116 donation from NLNet confirmed received:
118 ### Project 2019-02-012 28-apr-2020
120 - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
121 - 6600 scoreboard multi-read/write
123 - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
124 - Partitioned equals and greater than comparison
125 - Shared 50% with [[mnolan]]
127 - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
128 - partitioned scalar/vector shift
129 - Shared 50% with [[lkcl]]
132 ### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
134 - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
135 - auto-parser of POWER9
136 - Shared 50% with [[mnolan]]
139 ### Project 2019-10-029 Date 14mar2020
141 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
143 ### Project 2019-02-012 Date 12mar2020
145 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
146 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
147 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
148 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
150 ### Project 2019-02-012 Date 28jan2020
153 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>