llvm_vector_backend.mdwn

   1 # LLVM Backend Array Register Files
   2
   3 This backend is for expressing scenarios where registers have multiple
   4 potential overlapping meanings and uses, including but not limited to:
   5
   6 * **MMX / SSE / SIMD**: same registers of fixed length can be subdivided into
   7   multiple different SIMD elements, depending on the opcode used (or
   8   special CSRs - Control Status Registers)
   9 * **Virtual register redirection**: setting a CSR changes
  10   the meaning of instruction opcodes to access different "banks".
  11 * **Special register types**: expression of special register types,
  12   not just integer and float, but shader types for use in 3D, or
  13   Galois Field (GF).
  14 * Variations and combinations of the above
  15
  16 # Data Structures
  17
  18 ## Array Register File
  19
  20 This is for being able to express remapping / retargetting / redirection
  21 schemes that a microarchitecture has.
  22
  23     typedef struct {
  24         start: 12; // starting index of the "register"
  25         end: 12; // ending index of the "register" (inclusive)
  26         id: 8; // type of register: e.g 0=float, 1=int, 2=...
  27     } ARF;
  28
  29 Examples:
  30
  31     ARF1 = 0x01009005
  32     ARF2 = 0x0100a006
  33     ARF3 = 0x0100b008
  34
  35 These would indicate that when the (virtual) register ARF1 is used,
  36 it is of type "integer", and it requires the reservation of the **real**
  37 registers 5 through 9 at the hardware level.
  38
  39 ## Base Register Class
  40
  41     typedef struct {
  42         ARF: arf;  // the Array Register File identifier
  43         min: 12;   // if an opcode restricts the available range, use this
  44         max: 12;   // ... and this
  45         size: 8;   // the element bitwidth. e.g. 0=8, 1=16, 2=32.. TBD
  46         align: 4;  // an aligment restriction, in powers of 2.
  47     } BRC;
  48
  49 Examples:
  50
  51     A Compressed instruction from SV has restrictions on the
  52     range it may cover (unless redirection is taken into account).
  53     It is also possible to specify a bitwidth of 16, and if that is
  54     done, alignment has to be restricted to 4.  So:
  55
  56     brc1 = {
  57         arf = 0x0100b008; // integer register, using "real" regs 8-11 inclusive
  58         min = 8;          // C-type instructions go from 8-15 in the opcode
  59         max = 15;
  60         size = 0x1        // 1=16-bit (?)
  61         align: 2          // 2= 1<<2 (=4) because the "real" regs are 64-bit.
  62     };
  63
  64 ## Register Class Unions
  65
  66 Register Classes are the union of multiple Base Register Classes
  67 and traditional register classes.  In this way, all possible meanings
  68 and uses to which registers may be put can be expressed in one structure.
  69
  70 # Examples per Implementor
  71
  72 ## Array Register File
  73
  74 ### SimpleV
  75
  76 ### AMDGPU
  77
  78 ## Base Register Class
  79
  80 ### SimpleV
  81
  82 ### AMDGPU
  83
  84 ## Register Class Unions
  85
  86 ### SimpleV
  87
  88 ### AMDGPU
  89