2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
11 -- We calculate the address in the first cycle
18 l_in : in Execute1ToLoadstore1Type;
19 l_out : out Loadstore1ToWritebackType;
21 d_out : out Loadstore1ToDcacheType;
22 d_in : in DcacheToLoadstore1Type;
24 dc_stall : in std_ulogic;
25 stall_out : out std_ulogic
29 -- Note, we don't currently use the stall output from the dcache because
30 -- we know it can take two requests without stalling when idle, we are
31 -- its only user, and we know it never stalls when idle.
33 architecture behave of loadstore1 is
35 -- State machine for unaligned loads/stores
36 type state_t is (IDLE, -- ready for instruction
37 SECOND_REQ, -- send 2nd request of unaligned xfer
38 FIRST_ACK_WAIT, -- waiting for 1st ack from dcache
39 LAST_ACK_WAIT, -- waiting for last ack from dcache
40 LD_UPDATE -- writing rA with computed addr on load
43 type reg_stage_t is record
44 -- latch most of the input request
47 addr : std_ulogic_vector(63 downto 0);
48 store_data : std_ulogic_vector(63 downto 0);
49 load_data : std_ulogic_vector(63 downto 0);
50 write_reg : gpr_index_t;
51 length : std_ulogic_vector(3 downto 0);
52 byte_reverse : std_ulogic;
53 sign_extend : std_ulogic;
55 update_reg : gpr_index_t;
59 nc : std_ulogic; -- non-cacheable access
61 second_bytes : std_ulogic_vector(7 downto 0);
64 type byte_sel_t is array(0 to 7) of std_ulogic;
65 subtype byte_trim_t is std_ulogic_vector(1 downto 0);
66 type trim_ctl_t is array(0 to 7) of byte_trim_t;
68 signal r, rin : reg_stage_t;
69 signal lsu_sum : std_ulogic_vector(63 downto 0);
71 -- Generate byte enables from sizes
72 function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
86 end function length_to_sel;
88 -- Calculate byte enables
89 -- This returns 16 bits, giving the select signals for two transfers,
90 -- to account for unaligned loads or stores
91 function xfer_data_sel(size : in std_logic_vector(3 downto 0);
92 address : in std_logic_vector(2 downto 0))
93 return std_ulogic_vector is
94 variable longsel : std_ulogic_vector(15 downto 0);
96 longsel := "00000000" & length_to_sel(size);
97 return std_ulogic_vector(shift_left(unsigned(longsel),
98 to_integer(unsigned(address))));
99 end function xfer_data_sel;
102 -- Calculate the address in the first cycle
103 lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
105 loadstore1_0: process(clk)
107 if rising_edge(clk) then
116 loadstore1_1: process(all)
117 variable v : reg_stage_t;
118 variable brev_lenm1 : unsigned(2 downto 0);
119 variable byte_offset : unsigned(2 downto 0);
120 variable j : integer;
121 variable k : unsigned(2 downto 0);
122 variable kk : unsigned(3 downto 0);
123 variable long_sel : std_ulogic_vector(15 downto 0);
124 variable byte_sel : std_ulogic_vector(7 downto 0);
125 variable req : std_ulogic;
126 variable stall : std_ulogic;
127 variable addr : std_ulogic_vector(63 downto 0);
128 variable wdata : std_ulogic_vector(63 downto 0);
129 variable write_enable : std_ulogic;
130 variable do_update : std_ulogic;
131 variable two_dwords : std_ulogic;
132 variable done : std_ulogic;
133 variable data_permuted : std_ulogic_vector(63 downto 0);
134 variable data_trimmed : std_ulogic_vector(63 downto 0);
135 variable use_second : byte_sel_t;
136 variable trim_ctl : trim_ctl_t;
137 variable negative : std_ulogic;
143 byte_sel := (others => '0');
148 two_dwords := or (r.second_bytes);
150 -- load data formatting
151 byte_offset := unsigned(r.addr(2 downto 0));
153 if r.byte_reverse = '1' then
154 brev_lenm1 := unsigned(r.length(2 downto 0)) - 1;
157 -- shift and byte-reverse data bytes
159 kk := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
160 use_second(i) := kk(3);
161 j := to_integer(kk(2 downto 0)) * 8;
162 data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
165 -- Work out the sign bit for sign extension.
166 -- Assumes we are not doing both sign extension and byte reversal,
167 -- in that for unaligned loads crossing two dwords we end up
168 -- using a bit from the second dword, whereas for a byte-reversed
169 -- (i.e. big-endian) load the sign bit would be in the first dword.
170 negative := (r.length(3) and data_permuted(63)) or
171 (r.length(2) and data_permuted(31)) or
172 (r.length(1) and data_permuted(15)) or
173 (r.length(0) and data_permuted(7));
175 -- trim and sign-extend
177 if i < to_integer(unsigned(r.length)) then
178 if two_dwords = '1' then
179 trim_ctl(i) := '1' & not use_second(i);
181 trim_ctl(i) := not use_second(i) & '0';
184 trim_ctl(i) := '0' & (negative and r.sign_extend);
188 data_trimmed(i * 8 + 7 downto i * 8) := r.load_data(i * 8 + 7 downto i * 8);
190 data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
192 data_trimmed(i * 8 + 7 downto i * 8) := x"FF";
194 data_trimmed(i * 8 + 7 downto i * 8) := x"00";
200 if l_in.valid = '1' then
203 if l_in.op = OP_LOAD then
205 elsif l_in.op = OP_DCBZ then
209 v.write_reg := l_in.write_reg;
210 v.length := l_in.length;
211 v.byte_reverse := l_in.byte_reverse;
212 v.sign_extend := l_in.sign_extend;
213 v.update := l_in.update;
214 v.update_reg := l_in.update_reg;
216 v.reserve := l_in.reserve;
220 -- XXX Temporary hack. Mark the op as non-cachable if the address
221 -- is the form 0xc-------
223 -- This will have to be replaced by a combination of implementing the
224 -- proper HV CI load/store instructions and having an MMU to get the I
226 if lsu_sum(31 downto 28) = "1100" then
230 -- Do length_to_sel and work out if we are doing 2 dwords
231 long_sel := xfer_data_sel(l_in.length, v.addr(2 downto 0));
232 byte_sel := long_sel(7 downto 0);
233 v.second_bytes := long_sel(15 downto 8);
237 -- Do byte reversing and rotating for stores in the first cycle
238 byte_offset := unsigned(lsu_sum(2 downto 0));
240 if l_in.byte_reverse = '1' then
241 brev_lenm1 := unsigned(l_in.length(2 downto 0)) - 1;
244 k := (to_unsigned(i, 3) xor brev_lenm1) + byte_offset;
245 j := to_integer(k) * 8;
246 v.store_data(j + 7 downto j) := l_in.data(i * 8 + 7 downto i * 8);
251 if long_sel(15 downto 8) = "00000000" then
252 v.state := LAST_ACK_WAIT;
254 v.state := SECOND_REQ;
259 -- compute (addr + 8) & ~7 for the second doubleword when unaligned
260 addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
261 byte_sel := r.second_bytes;
264 v.state := FIRST_ACK_WAIT;
266 when FIRST_ACK_WAIT =>
268 if d_in.valid = '1' then
269 v.state := LAST_ACK_WAIT;
271 v.load_data := data_permuted;
275 when LAST_ACK_WAIT =>
277 if d_in.valid = '1' then
278 write_enable := r.load;
279 if r.load = '1' and r.update = '1' then
280 -- loads with rA update need an extra cycle
281 v.state := LD_UPDATE;
283 -- stores write back rA update in this cycle
284 do_update := r.update;
297 -- Update outputs to dcache
299 d_out.load <= v.load;
300 d_out.dcbz <= v.dcbz;
302 d_out.reserve <= v.reserve;
304 d_out.data <= v.store_data;
305 d_out.byte_sel <= byte_sel;
307 -- Update outputs to writeback
308 -- Multiplex either cache data to the destination GPR or
309 -- the address for the rA update.
311 if do_update = '1' then
312 l_out.write_enable <= '1';
313 l_out.write_reg <= r.update_reg;
314 l_out.write_data <= r.addr;
316 l_out.write_enable <= write_enable;
317 l_out.write_reg <= r.write_reg;
318 l_out.write_data <= data_trimmed;
320 l_out.xerc <= r.xerc;
321 l_out.rc <= r.rc and done;
322 l_out.store_done <= d_in.store_done;