loadstore1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.helpers.all;
   8
   9 -- 2 cycle LSU
  10 -- We calculate the address in the first cycle
  11
  12 entity loadstore1 is
  13     port (
  14         clk   : in std_ulogic;
  15
  16         l_in  : in Decode2ToLoadstore1Type;
  17
  18         l_out : out Loadstore1ToLoadstore2Type
  19         );
  20 end loadstore1;
  21
  22 architecture behave of loadstore1 is
  23     signal r, rin : Loadstore1ToLoadstore2Type;
  24     signal lsu_sum : std_ulogic_vector(63 downto 0);
  25 begin
  26     -- Calculate the address in the first cycle
  27     lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
  28
  29     loadstore1_0: process(clk)
  30     begin
  31         if rising_edge(clk) then
  32             r <= rin;
  33         end if;
  34     end process;
  35
  36     loadstore1_1: process(all)
  37         variable v : Loadstore1ToLoadstore2Type;
  38     begin
  39         v := r;
  40
  41         v.valid := l_in.valid;
  42         v.load := l_in.load;
  43         v.data := l_in.data;
  44         v.write_reg := l_in.write_reg;
  45         v.length := l_in.length;
  46         v.byte_reverse := l_in.byte_reverse;
  47         v.sign_extend := l_in.sign_extend;
  48         v.update := l_in.update;
  49         v.update_reg := l_in.update_reg;
  50
  51         -- byte reverse stores in the first cycle
  52         if v.load = '0' and l_in.byte_reverse = '1' then
  53             v.data := byte_reverse(l_in.data, to_integer(unsigned(l_in.length)));
  54         end if;
  55
  56         v.addr := lsu_sum;
  57
  58         -- Update registers
  59         rin <= v;
  60
  61         -- Update outputs
  62         l_out <= r;
  63     end process;
  64 end;