2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
10 -- We calculate the address in the first cycle
16 l_in : in Decode2ToLoadstore1Type;
18 l_out : out Loadstore1ToDcacheType
22 architecture behave of loadstore1 is
23 signal r, rin : Loadstore1ToDcacheType;
24 signal lsu_sum : std_ulogic_vector(63 downto 0);
26 -- Calculate the address in the first cycle
27 lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
29 loadstore1_0: process(clk)
31 if rising_edge(clk) then
36 loadstore1_1: process(all)
37 variable v : Loadstore1ToDcacheType;
41 v.valid := l_in.valid;
44 v.write_reg := l_in.write_reg;
45 v.length := l_in.length;
46 v.byte_reverse := l_in.byte_reverse;
47 v.sign_extend := l_in.sign_extend;
48 v.update := l_in.update;
49 v.update_reg := l_in.update_reg;
51 -- XXX Temporary hack. Mark the op as non-cachable if the address
52 -- is the form 0xc-------
54 -- This will have to be replaced by a combination of implementing the
55 -- proper HV CI load/store instructions and having an MMU to get the I
57 if lsu_sum(31 downto 28) = "1100" then
63 -- XXX Do length_to_sel here ?
65 -- byte reverse stores in the first cycle
66 if v.load = '0' and l_in.byte_reverse = '1' then
67 v.data := byte_reverse(l_in.data, to_integer(unsigned(l_in.length)));