2 from cocotb
.clock
import Clock
3 from cocotb
.triggers
import Timer
4 from cocotb
.utils
import get_sim_steps
5 from cocotb
.binary
import BinaryValue
7 from c4m
.cocotb
.jtag
.c4m_jtag
import JTAG_Master
8 from c4m
.cocotb
.jtag
.c4m_jtag_svfcocotb
import SVF_Executor
10 from itertools
import chain
13 from cocotb
.clock
import Clock
14 from cocotb
.triggers
import Timer
15 from cocotb
.utils
import get_sim_steps
16 from cocotb
.binary
import BinaryValue
18 from c4m
.nmigen
.jtag
.tap
import IOType
19 from c4m
.cocotb
.jtag
.c4m_jtag
import JTAG_Master
20 from c4m
.cocotb
.jtag
.c4m_jtag_svfcocotb
import SVF_Executor
22 from soc
.config
.pinouts
import get_pinspecs
23 from soc
.debug
.jtag
import Pins
29 def setup_sim(dut
, *, clk_period
, run
):
30 """Initialize CPU and setup clock"""
32 clk_steps
= get_sim_steps(clk_period
, "ns")
33 cocotb
.fork(Clock(dut
.sys_clk
, clk_steps
).start())
41 # adder test (ignore this)
46 yield Timer(int(10.5*clk_steps
))
48 yield Timer(int(5*clk_steps
))
50 def setup_jtag(dut
, *, tck_period
):
51 # Make this a generator
54 clk_steps
= get_sim_steps(tck_period
, "ns")
55 return JTAG_Master(dut
.jtag_tck
, dut
.jtag_tms
,
56 dut
.jtag_tdi
, dut
.jtag_tdo
,
60 def execute_svf(dut
, *, jtag
, svf_filename
):
61 jtag_svf
= SVF_Executor(jtag
)
62 with
open(svf_filename
, "r") as f
:
64 yield jtag_svf
.run(svf_deck
, p
=dut
._log
.info
)
67 # IDCODE using JTAG_master
70 def idcode(dut
, *, jtag
):
71 #jtag.IDCODE = [0, 0, 0, 1]
74 dut
._log
.info("IDCODE1: {}".format(result1
))
75 assert(result1
== BinaryValue("00000000000000000001100011111111"))
79 dut
._log
.info("IDCODE2: {}".format(result2
))
81 assert(result1
== result2
)
84 def idcode_reset(dut
):
85 dut
._log
.info("Running IDCODE test; cpu in reset...")
87 clk_period
= 100 # 10MHz
88 tck_period
= 300 # 3MHz
90 yield from setup_sim(dut
, clk_period
=clk_period
, run
=False)
91 jtag
= yield from setup_jtag(dut
, tck_period
= tck_period
)
93 yield from idcode(dut
, jtag
=jtag
)
95 dut
._log
.info("IDCODE test completed")
99 dut
._log
.info("Running IDCODE test; cpu running...")
101 clk_period
= 100 # 10MHz
102 tck_period
= 300 # 3MHz
104 yield from setup_sim(dut
, clk_period
=clk_period
, run
=True)
105 jtag
= yield from setup_jtag(dut
, tck_period
= tck_period
)
107 yield from idcode(dut
, jtag
=jtag
)
109 dut
._log
.info("IDCODE test completed")
112 # Read IDCODE from SVF file
116 def idcodesvf_reset(dut
):
117 dut
._log
.info("Running IDCODE through SVF test; cpu in reset...")
119 clk_period
= 100 # 10MHz
120 tck_period
= 300 # 3MHz
122 yield from setup_sim(dut
, clk_period
=clk_period
, run
=False)
123 jtag
= yield from setup_jtag(dut
, tck_period
= tck_period
)
125 yield from execute_svf(dut
, jtag
=jtag
, svf_filename
="idcode.svf")
127 dut
._log
.info("IDCODE test completed")
130 def idcode_run_svf(dut
):
131 dut
._log
.info("Running IDCODE through test; cpu running...")
133 clk_period
= 100 # 10MHz
134 tck_period
= 300 # 3MHz
136 yield from setup_sim(dut
, clk_period
=clk_period
, run
=True)
137 jtag
= yield from setup_jtag(dut
, tck_period
= tck_period
)
139 yield from execute_svf(dut
, jtag
=jtag
, svf_filename
="idcode.svf")
141 dut
._log
.info("IDCODE test completed")
145 def wishbone_basic(dut
):
147 Test of an added Wishbone interface
149 clk_period
= 100 # 100MHz
150 tck_period
= 3000 # 0.3MHz
152 data_in
= BinaryValue()
153 # these have to match with soc.debug.jtag.JTAG ircodes
154 cmd_MEMADDRESS
= BinaryValue("0101") # 5
155 cmd_MEMREAD
= BinaryValue("0110") # 6
156 cmd_MEMREADWRITE
= BinaryValue("0111") # 7
158 info
= "Running Wishbone basic test"
159 yield from setup_sim(dut
, clk_period
=clk_period
, run
=True)
160 master
= yield from setup_jtag(dut
, tck_period
= tck_period
)
162 # Load the memory address
163 yield master
.load_ir(cmd_MEMADDRESS
)
164 dut
._log
.info("Loading address")
166 data_in
.binstr
= "000000000000000000000000000001"
167 dut
._log
.info(" input: {}".format(data_in
.binstr
))
168 yield master
.shift_data(data_in
)
169 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
172 yield master
.load_ir(cmd_MEMREADWRITE
)
173 dut
._log
.info("Writing memory")
175 data_in
.binstr
= "01010101" * 4
176 dut
._log
.info(" input: {}".format(data_in
.binstr
))
177 yield master
.shift_data(data_in
)
178 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
180 data_in
.binstr
= "10101010" * 4
181 dut
._log
.info(" input: {}".format(data_in
.binstr
))
182 yield master
.shift_data(data_in
)
183 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
185 # Load the memory address
186 yield master
.load_ir(cmd_MEMADDRESS
)
187 dut
._log
.info("Loading address")
189 data_in
.binstr
= "000000000000000000000000000001"
190 dut
._log
.info(" input: {}".format(data_in
.binstr
))
191 yield master
.shift_data(data_in
)
192 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
193 assert master
.result
.binstr
== "000000000000000000000000000011"
196 yield master
.load_ir(cmd_MEMREADWRITE
)
197 dut
._log
.info("Reading and writing memory")
199 data_in
.binstr
= "10101010" * 4
200 dut
._log
.info(" input: {}".format(data_in
.binstr
))
201 yield master
.shift_data(data_in
)
202 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
203 assert master
.result
.binstr
== "01010101" * 4
205 data_in
.binstr
= "01010101" * 4
206 dut
._log
.info(" input: {}".format(data_in
.binstr
))
207 yield master
.shift_data(data_in
)
208 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
209 assert master
.result
.binstr
== "10101010" * 4
211 # Load the memory address
212 yield master
.load_ir(cmd_MEMADDRESS
)
213 dut
._log
.info("Loading address")
215 data_in
.binstr
= "000000000000000000000000000001"
216 dut
._log
.info(" input: {}".format(data_in
.binstr
))
217 yield master
.shift_data(data_in
)
218 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
219 assert master
.result
.binstr
== "000000000000000000000000000011"
222 yield master
.load_ir(cmd_MEMREAD
)
223 dut
._log
.info("Reading memory")
224 data_in
.binstr
= "00000000" * 4
226 dut
._log
.info(" input: {}".format(data_in
.binstr
))
227 yield master
.shift_data(data_in
)
228 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
229 assert master
.result
.binstr
== "10101010" * 4
231 dut
._log
.info(" input: {}".format(data_in
.binstr
))
232 yield master
.shift_data(data_in
)
233 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
234 assert master
.result
.binstr
== "01010101" * 4
236 # Load the memory address
237 yield master
.load_ir(cmd_MEMADDRESS
) # MEMADDR
238 dut
._log
.info("Loading address")
240 data_in
.binstr
= "000000000000000000000000000001"
241 dut
._log
.info(" input: {}".format(data_in
.binstr
))
242 yield master
.shift_data(data_in
)
243 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
244 assert master
.result
.binstr
== "000000000000000000000000000011"
247 yield master
.load_ir(cmd_MEMREAD
) # MEMREAD
248 dut
._log
.info("Reading memory")
249 data_in
.binstr
= "00000000" * 4
251 dut
._log
.info(" input: {}".format(data_in
.binstr
))
252 yield master
.shift_data(data_in
)
253 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
254 assert master
.result
.binstr
== "10101010" * 4
256 dut
._log
.info(" input: {}".format(data_in
.binstr
))
257 yield master
.shift_data(data_in
)
258 dut
._log
.info(" output: {}".format(master
.result
.binstr
))
259 assert master
.result
.binstr
== "01010101" * 4
261 #dut._log.info("{!r}".format(wbmem))
264 # demo / debug how to get boundary scan names. run "python3 test.py"
265 if __name__
== '__main__':
266 pinouts
= get_jtag_boundary()
268 # example: ('eint', '2', <IOType.In: 1>, 'eint_2', 125)