lxo/550/libresoc-svp64-prefix-imm24.patch

   1 Libre-SOC: introduce svp64 prefix
   2
   3 From: Alexandre Oliva <oliva@gnu.org>
   4
   5 This patch introduces a first cut at an "svp64" prefix for Libre-SOC
   6 PPC, in which all of its non-contiguous 24 bits of operands are
   7 specified as a single 24-bit immediate.
   8
   9
  10 for  opcodes/ChangeLog
  11
  12         * ppc-opc.c (insert_svp64imm24, extract_svp64imm24): New.
  13         (SVP64IMM24): Define.
  14         (powerpc_operands): Add it.
  15         (LIBRESOC): Add dummy definition.
  16         (powerpc_opcodes): Add svp64 prefix, as a pseudo-insn.
  17
  18 for  gas/ChangeLog
  19
  20         * testsuite/gas/ppc/svp64.s: New.
  21         * testsuite/gas/ppc/svp64.d: New.
  22         * testsuite/gas/ppc/ppc.exp: Add it.
  23 ---
  24  gas/testsuite/gas/ppc/ppc.exp |    3 +++
  25  gas/testsuite/gas/ppc/svp64.d |   20 ++++++++++++++++++++
  26  gas/testsuite/gas/ppc/svp64.s |   10 ++++++++++
  27  opcodes/ppc-opc.c             |   41 +++++++++++++++++++++++++++++++++++++++--
  28  4 files changed, 72 insertions(+), 2 deletions(-)
  29  create mode 100644 gas/testsuite/gas/ppc/svp64.d
  30  create mode 100644 gas/testsuite/gas/ppc/svp64.s
  31
  32 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
  33 index 561b2b4ed3098..84f9daff6e813 100644
  34 --- a/gas/testsuite/gas/ppc/ppc.exp
  35 +++ b/gas/testsuite/gas/ppc/ppc.exp
  36 @@ -148,3 +148,6 @@ run_dump_test "rightmost"
  37  run_dump_test "scalarquad"
  38
  39  run_dump_test "dcbt"
  40 +
  41 +# Libre-SOC
  42 +run_dump_test "svp64"
  43 diff --git a/gas/testsuite/gas/ppc/svp64.d b/gas/testsuite/gas/ppc/svp64.d
  44 new file mode 100644
  45 index 0000000000000..ceddabd0e2beb
  46 --- /dev/null
  47 +++ b/gas/testsuite/gas/ppc/svp64.d
  48 @@ -0,0 +1,20 @@
  49 +#as:
  50 +#objdump: -dr
  51 +#name: LibreSOC SVP64 test
  52 +
  53 +.*
  54 +
  55 +
  56 +Disassembly of section \.text:
  57 +
  58 +0+00 <svp64>:
  59 +
  60 +.*:    (05 40 00 00|00 00 40 05)       svp64   0
  61 +.*:    (60 00 00 00|00 00 00 60)       nop
  62 +.*:    (07 ff ff ff|ff ff ff 07)       svp64   16777215
  63 +.*:    (60 00 00 00|00 00 00 60)       nop
  64 +.*:    (07 55 c3 6a|6a c3 55 07)       svp64   9814890
  65 +.*:    (60 00 00 00|00 00 00 60)       nop
  66 +.*:    (05 ea 3c 95|95 3c ea 05)       svp64   6962325
  67 +.*:    (60 00 00 00|00 00 00 60)       nop
  68 +#pass
  69 diff --git a/gas/testsuite/gas/ppc/svp64.s b/gas/testsuite/gas/ppc/svp64.s
  70 new file mode 100644
  71 index 0000000000000..c935f1e0b5487
  72 --- /dev/null
  73 +++ b/gas/testsuite/gas/ppc/svp64.s
  74 @@ -0,0 +1,10 @@
  75 +       .text
  76 +svp64:
  77 +       svp64 0
  78 +       nop
  79 +       svp64 0xffffff
  80 +       nop
  81 +       svp64 0x95c36a
  82 +       nop
  83 +       svp64 0x6a3c95
  84 +       nop
  85 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
  86 index f23d142c0e147..86ae3c8d577b6 100644
  87 --- a/opcodes/ppc-opc.c
  88 +++ b/opcodes/ppc-opc.c
  89 @@ -643,6 +643,33 @@ extract_nsi34 (uint64_t insn,
  90    return -value;
  91  }
  92
  93 +/* The non-contiguous 24-bits of operands in a svp64 prefix.  */
  94 +static uint64_t
  95 +insert_svp64imm24 (uint64_t insn,
  96 +                  int64_t value,
  97 +                  ppc_cpu_t dialect ATTRIBUTE_UNUSED,
  98 +                  const char **errmsg ATTRIBUTE_UNUSED)
  99 +{
 100 +  if (value & ~(int64_t)0xffffff)
 101 +    *errmsg = _("illegal immediate value");
 102 +
 103 +  return insn
 104 +    | ((value & 0x800000) << 2)
 105 +    | ((value & 0x400000) << 1)
 106 +    |  (value & 0x3fffff);
 107 +}
 108 +
 109 +static int64_t
 110 +extract_svp64imm24 (uint64_t insn,
 111 +                   ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 112 +                   int *invalid ATTRIBUTE_UNUSED)
 113 +{
 114 +  return 0
 115 +    | ((insn & 0x2000000) >> 2)
 116 +    | ((insn & 0x0800000) >> 1)
 117 +    | ((insn & 0x03fffff));
 118 +}
 119 +
 120  /* The split IMM32 field in a vector splat insn.  */
 121
 122  static uint64_t
 123 @@ -2451,8 +2478,15 @@ const struct powerpc_operand powerpc_operands[] =
 124    { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34,
 125      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 126
 127 +  /* The 24 non-contiguous bits that encode the operands for an SVP64
 128 +     prefix.  */
 129 +#define SVP64IMM24 NSI34 + 1
 130 +  /*0x2bfffff is the actual mask, but some pieces of the assembler
 131 +    require a contiguous bit pattern.  */
 132 +  { 0x3ffffff, PPC_OPSHIFT_INV, insert_svp64imm24, extract_svp64imm24, 0},
 133 +
 134    /* The IMM32 field in a vector splat immediate prefix instruction.  */
 135 -#define IMM32 NSI34 + 1
 136 +#define IMM32 SVP64IMM24 + 1
 137    { 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0},
 138
 139    /* The UIM field in a vector permute extended prefix instruction.  */
 140 @@ -4215,7 +4249,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 141     for the 3 operand dcbt and dcbtst instructions.  */
 142  #define DCBT_EO        (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
 143                  | PPC_OPCODE_A2)
 144 -
 145 +#define LIBRESOC PPC /* FIXME */
 146
 147  \f
 148  /* The opcode table.
 149 @@ -4242,6 +4276,9 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 150
 151  const struct powerpc_opcode powerpc_opcodes[] = {
 152  {"attn",       X(0,256),       X_MASK,   POWER4|PPCA2, PPC476|PPCVLE,  {0}},
 153 +
 154 +{"svp64",      0x05400000,     0xfd400000,  LIBRESOC,  PPCVLE,         {SVP64IMM24}},
 155 +
 156  {"tdlgti",     OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
 157  {"tdllti",     OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
 158  {"tdeqi",      OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},